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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH] target/riscv/vector_helper.c: clean up reference of MTYPE Content-Language: en-US To: Xiao Wang , qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , "open list:RISC-V TCG CPUs" References: <20230608053517.4102648-1-xiao.w.wang@intel.com> From: Daniel Henrique Barboza In-Reply-To: <20230608053517.4102648-1-xiao.w.wang@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x32.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 6/8/23 02:35, Xiao Wang wrote: > There's no code using MTYPE, which was a concept used in older vector > implementation. > > Signed-off-by: Xiao Wang > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/vector_helper.c | 6 +----- > 1 file changed, 1 insertion(+), 5 deletions(-) > > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index f261e726c2..1e06e7447c 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -378,7 +378,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, > > /* > * masked unit-stride load and store operation will be a special case of > - * stride, stride = NF * sizeof (MTYPE) > + * stride, stride = NF * sizeof (ETYPE) > */ > > #define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN) \ > @@ -650,10 +650,6 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d) > #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) > #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) > > -/* Unsigned min/max */ > -#define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M) > -#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M) > - > /* > * load and store whole register instructions > */