Re: [Qemu-devel] [PATCH v2] piix: define a TOM register to report the base of PCI

["Andreas Färber" <afaerber@suse.de>]

Am 18.03.2013 16:21, schrieb Hao, Xudong:
>> -----Original Message-----
>> From: Michael S. Tsirkin [mailto:mst@redhat.com]
>> Sent: Wednesday, February 27, 2013 6:50 PM
>> To: Hao, Xudong
>> Cc: aliguori@us.ibm.com; qemu-devel@nongnu.org;
>> stefano.stabellini@eu.citrix.com; xen-devel@lists.xen.org; afaerber@suse.de;
>> JBeulich@suse.com; Zhang, Xiantao
>> Subject: Re: [PATCH v2] piix: define a TOM register to report the base of PCI
>>
>> On Mon, Feb 25, 2013 at 02:53:37PM +0800, Xudong Hao wrote:
>>> v2:
>>> * Use "piix: " in the subject rather than "qemu: "
>>> * Define TOM register as one byte
>>> * Define default TOM value instead of hardcode 0xe0000000 in more that one
>> place
>>> * Use API pci_set_byte for pci config access
>>> * Use dev->config instead of the indirect d->dev.config
>>>
>>> Define a TOM(top of memory) register to report the base of PCI memory,
>> update
>>> memory region dynamically. TOM register are defined to one byte in PCI
>> configure
>>> space, because that only upper 4 bit of PCI memory takes effect for Xen, so
>>> it requires bios set TOM with 16M-aligned.
>>>
>>> Signed-off-by: Xudong Hao <xudong.hao@intel.com>
>>> Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
>>
>> Could you supply some motivation for this patch?
>>
> 
> It's a fix for Xen. Qemu want more information from Xen, copy Stefano's comments:
> 
> QEMU needs to know where the end of the guest's RAM is (because there is
> where it allocates the videoram and other stuff), so at least the size
> of the MMIO hole is important.

Could you please reply to Anthony's comment that this information is
already available via fw_cfg interface? hw/fw_cfg.h is designed so that
it can be embedded elsewhere (e.g., in SeaBIOS and OpenBIOS). Reusing
any information available through that interface would seem much easier
than fiddling with reserved registers on emulated hardware.

Regards,
Andreas

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