From: Stephen Boyd <sboyd@codeaurora.org>
To: Will Deacon <will.deacon@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-msm@vger.kernel.org" <linux-arm-msm@vger.kernel.org>,
Stepan Moskovchenko <stepanm@codeaurora.org>
Subject: Re: [PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs
Date: Mon, 18 Mar 2013 10:03:49 -0700 [thread overview]
Message-ID: <514748F5.70504@codeaurora.org> (raw)
In-Reply-To: <20130317142854.GC19071@mudshark.cambridge.arm.com>
On 03/17/13 07:28, Will Deacon wrote:
> On Wed, Mar 13, 2013 at 01:32:01AM +0000, Stephen Boyd wrote:
>> Some early versions of the Krait CPU design incorrectly indicate
>> that they only support the UDIV and SDIV instructions in Thumb
>> mode when they actually support them in ARM and Thumb mode. It
>> seems that these CPUs follow the DDI0406B ARM ARM which has two
>> possible values for the divide instructions field, instead of the
>> DDI0406C document which has three possible values.
>>
>> Work around this problem by checking the MIDR against Krait CPUs
>> with this faulty ISAR0 register and force the detection code
>> to indicate support in both modes.
>>
>> Cc: Will Deacon <will.deacon@arm.com>
>> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>> arch/arm/kernel/setup.c | 8 ++++++++
>> 1 file changed, 8 insertions(+)
> After all this, you might as well just pass the relevant HWCAPs for your
> krait entry in proc-v7.S rather than have an exception in the CPU-agnostic
> code.
Ok. Care to ack the previous patch I sent then?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs
Date: Mon, 18 Mar 2013 10:03:49 -0700 [thread overview]
Message-ID: <514748F5.70504@codeaurora.org> (raw)
In-Reply-To: <20130317142854.GC19071@mudshark.cambridge.arm.com>
On 03/17/13 07:28, Will Deacon wrote:
> On Wed, Mar 13, 2013 at 01:32:01AM +0000, Stephen Boyd wrote:
>> Some early versions of the Krait CPU design incorrectly indicate
>> that they only support the UDIV and SDIV instructions in Thumb
>> mode when they actually support them in ARM and Thumb mode. It
>> seems that these CPUs follow the DDI0406B ARM ARM which has two
>> possible values for the divide instructions field, instead of the
>> DDI0406C document which has three possible values.
>>
>> Work around this problem by checking the MIDR against Krait CPUs
>> with this faulty ISAR0 register and force the detection code
>> to indicate support in both modes.
>>
>> Cc: Will Deacon <will.deacon@arm.com>
>> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>> arch/arm/kernel/setup.c | 8 ++++++++
>> 1 file changed, 8 insertions(+)
> After all this, you might as well just pass the relevant HWCAPs for your
> krait entry in proc-v7.S rather than have an exception in the CPU-agnostic
> code.
Ok. Care to ack the previous patch I sent then?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
next prev parent reply other threads:[~2013-03-18 17:03 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-13 1:31 [PATCH 0/3] Detect UDIV/SDIV support from ISAR0 Stephen Boyd
2013-03-13 1:31 ` Stephen Boyd
2013-03-13 1:31 ` [PATCH 1/3] ARM: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n Stephen Boyd
2013-03-13 1:31 ` Stephen Boyd
2013-03-13 1:31 ` Stephen Boyd
2013-03-17 14:29 ` Will Deacon
2013-03-17 14:29 ` Will Deacon
2013-03-13 1:32 ` [PATCH 2/3] ARM: Detect support for SDIV/UDIV from ISAR0 register Stephen Boyd
2013-03-13 1:32 ` Stephen Boyd
2013-03-17 14:36 ` Will Deacon
2013-03-17 14:36 ` Will Deacon
2013-03-18 17:13 ` Stephen Boyd
2013-03-18 17:13 ` Stephen Boyd
2013-03-13 1:32 ` [PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs Stephen Boyd
2013-03-13 1:32 ` Stephen Boyd
2013-03-17 14:28 ` Will Deacon
2013-03-17 14:28 ` Will Deacon
2013-03-18 17:03 ` Stephen Boyd [this message]
2013-03-18 17:03 ` Stephen Boyd
2013-03-18 18:19 ` Will Deacon
2013-03-18 18:19 ` Will Deacon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=514748F5.70504@codeaurora.org \
--to=sboyd@codeaurora.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=stepanm@codeaurora.org \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.