Re: [PATCH 3/4][net-next] gianfar: Remove redundant programming of [rt]xic registers

[Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>]

Hello.

On 19-03-2013 21:40, Claudiu Manoil wrote:

> For Multi Q Multi Group (MQ_MG_MODE) mode, the Rx/Tx colescing registers [rt]xic
> are aliased with the [rt]xic0 registers (coalescing setting regs for Q0). This
> avoids programming twice in a row the coalescing registers for the Rx/Tx hw Q0.

> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
> ---
>   drivers/net/ethernet/freescale/gianfar.c | 24 ++++++++++++------------
>   1 file changed, 12 insertions(+), 12 deletions(-)

> diff --git a/drivers/net/ethernet/freescale/gianfar.c b/drivers/net/ethernet/freescale/gianfar.c
> index 3f07dbd..e28b3e6 100644
> --- a/drivers/net/ethernet/freescale/gianfar.c
> +++ b/drivers/net/ethernet/freescale/gianfar.c
> @@ -1821,20 +1821,9 @@ void gfar_configure_coalescing(struct gfar_private *priv,
[...]
>   	if (priv->mode == MQ_MG_MODE) {
> +		int i = 0;

    Empty line wouldn't hurt here, after declaration.

>   		baddr = &regs->txic0;
>   		for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
>   			gfar_write(baddr + i, 0);
> @@ -1848,6 +1837,17 @@ void gfar_configure_coalescing(struct gfar_private *priv,
>   			if (likely(priv->rx_queue[i]->rxcoalescing))
>   				gfar_write(baddr + i, priv->rx_queue[i]->rxic);
>   		}
> +	} else {
> +		/* Backward compatible case ---- even if we enable

    s/----/--/

WBR, Sergei