From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:37888) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UILVq-0007tO-0e for qemu-devel@nongnu.org; Wed, 20 Mar 2013 12:05:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UILVo-0001wr-I5 for qemu-devel@nongnu.org; Wed, 20 Mar 2013 12:05:13 -0400 Received: from mel.act-europe.fr ([194.98.77.210]:40678) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UILVo-0001wG-Bq for qemu-devel@nongnu.org; Wed, 20 Mar 2013 12:05:12 -0400 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 988502900A6 for ; Wed, 20 Mar 2013 17:05:11 +0100 (CET) Received: from mel.act-europe.fr ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HpfXR3wgRyl9 for ; Wed, 20 Mar 2013 17:05:11 +0100 (CET) Received: from [10.10.1.88] (pompomgalli.act-europe.fr [10.10.1.88]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by mel.act-europe.fr (Postfix) with ESMTP id 7C0E2290009 for ; Wed, 20 Mar 2013 17:05:11 +0100 (CET) Message-ID: <5149DE36.3060301@adacore.com> Date: Wed, 20 Mar 2013 17:05:10 +0100 From: Fabien Chouteau MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] Cortex-M4F Floating Point system registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "qemu-devel@nongnu.org" Hello QEMU ARM folks, I'm looking at the ARMv7-M profile and the implementation in QEMU. Looks like M3 is supported and I'd like to work on M4F (FP context save and lazy FP context save). I wonder how the FPU system registers, and more generally how the co-processor registers are implemented in QEMU. For example in the Cortex-M4 TRM it seems like FP system registers are mapped in memory. I don't see that implemented in QEMU. Thanks, -- Fabien Chouteau