diff for duplicates of <51503183.2010609@nvidia.com> diff --git a/a/1.txt b/N1/1.txt index ffd8673..6862098 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -4,7 +4,7 @@ On Monday 25 March 2013 03:45 PM, Peter De Schrijver wrote: >>> The PLL code relies on udelay() which is not available when CCF is >>> initialized. Hence we can't enable any PLL during this phase. >>> ->>> Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +>>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> >>> >>> -- >>> diff --git a/a/content_digest b/N1/content_digest index bf516d7..63904d6 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,17 +1,10 @@ "ref\01363953308-28828-1-git-send-email-pdeschrijver@nvidia.com\0" "ref\0514C7D3B.40602@wwwdotorg.org\0" "ref\020130325101542.GB18519@tbergstrom-lnx.Nvidia.com\0" - "ref\020130325101542.GB18519-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org\0" - "From\0Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" - "Subject\0Re: [PATCH] clk: tegra: Don't enable PLLs during early boot\0" + "From\0pgaikwad@nvidia.com (Prashant Gaikwad)\0" + "Subject\0[PATCH] clk: tegra: Don't enable PLLs during early boot\0" "Date\0Mon, 25 Mar 2013 16:44:11 +0530\0" - "To\0Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" - "Cc\0Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>" - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> - Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> - Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org> - linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - " linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Monday 25 March 2013 03:45 PM, Peter De Schrijver wrote:\n" @@ -20,7 +13,7 @@ ">>> The PLL code relies on udelay() which is not available when CCF is\n" ">>> initialized. Hence we can't enable any PLL during this phase.\n" ">>>\n" - ">>> Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + ">>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>\n" ">>>\n" ">>> --\n" ">>>\n" @@ -70,4 +63,4 @@ ">\n" > Peter. -d3615861436416a46e24957bd7bb7f6d12ff72bbfb6b50dc7cd92c9f5af32b42 +f2ab3e6fa76fb0f72109de05408e02b3d8e948b092420e642c2d71dadb951f6a
diff --git a/a/1.txt b/N2/1.txt index ffd8673..6862098 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -4,7 +4,7 @@ On Monday 25 March 2013 03:45 PM, Peter De Schrijver wrote: >>> The PLL code relies on udelay() which is not available when CCF is >>> initialized. Hence we can't enable any PLL during this phase. >>> ->>> Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +>>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> >>> >>> -- >>> diff --git a/a/content_digest b/N2/content_digest index bf516d7..e52e074 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,17 +1,16 @@ "ref\01363953308-28828-1-git-send-email-pdeschrijver@nvidia.com\0" "ref\0514C7D3B.40602@wwwdotorg.org\0" "ref\020130325101542.GB18519@tbergstrom-lnx.Nvidia.com\0" - "ref\020130325101542.GB18519-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org\0" - "From\0Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" + "From\0Prashant Gaikwad <pgaikwad@nvidia.com>\0" "Subject\0Re: [PATCH] clk: tegra: Don't enable PLLs during early boot\0" "Date\0Mon, 25 Mar 2013 16:44:11 +0530\0" - "To\0Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" - "Cc\0Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>" - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> - Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> - Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org> - linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - " linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>\0" + "To\0Peter De Schrijver <pdeschrijver@nvidia.com>\0" + "Cc\0Stephen Warren <swarren@wwwdotorg.org>" + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + Mike Turquette <mturquette@linaro.org> + Thierry Reding <thierry.reding@avionic-design.de> + linux-tegra@vger.kernel.org <linux-tegra@vger.kernel.org> + " linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>\0" "\00:1\0" "b\0" "On Monday 25 March 2013 03:45 PM, Peter De Schrijver wrote:\n" @@ -20,7 +19,7 @@ ">>> The PLL code relies on udelay() which is not available when CCF is\n" ">>> initialized. Hence we can't enable any PLL during this phase.\n" ">>>\n" - ">>> Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + ">>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>\n" ">>>\n" ">>> --\n" ">>>\n" @@ -70,4 +69,4 @@ ">\n" > Peter. -d3615861436416a46e24957bd7bb7f6d12ff72bbfb6b50dc7cd92c9f5af32b42 +f143fa2df59fb7ab4e7b8b19466639d7f92c223fa972a0271eb234a507f7920e
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