Re: [Qemu-devel] [PATCH v3 08/20] tcg-arm: Implement deposit for armv7

[Richard Henderson <rth@twiddle.net>]

On 03/28/2013 09:15 AM, Peter Maydell wrote:
>> +    /* ??? Without bfi, we could improve over generic code by combining
>> +       the right-shift from a non-zero ofs with the orr.  We do run into
>> +       problems when rd == rs, and the mask generated from ofs+len don't
>> +       fit into an immediate.  We would have to be careful not to pessimize
>> +       wrt the optimizations performed on the expanded code.  */
>> +    return use_armv7_instructions;
> 
> Strictly speaking BFI is v6T2, but there doesn't seem much point
> in making the distinction given it would only affect the rare
> ARM1156. (Personally I don't think there's much point worrying about
> optmising codegen for anything pre-v7 at all.)

Fair enough.  I could update the comment to include v6t2, since I've done
similar for e.g. v6k (while retaining the v7 test) elsewhere in the patch set.

> What guarantees us that we won't see a length of 0?
> The tcg/README description doesn't say that's invalid
> and I don't think the optimize pass handles it (maybe I
> missed it).

We can patch the readme, and the asserts in tcg-op.h if you like.

I've assumed elsewhere that we won't see a zero length.  E.g. none of the other
cpus -- ppc, hppa, ia64 -- can encode that either.


r~