From: Stephen Warren <swarren@wwwdotorg.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] Tegra: Fix MSELECT clock divisors for T30/T114.
Date: Wed, 03 Apr 2013 17:28:00 -0600 [thread overview]
Message-ID: <515CBB00.2010608@wwwdotorg.org> (raw)
In-Reply-To: <1365031032-12739-1-git-send-email-twarren@nvidia.com>
On 04/03/2013 05:17 PM, Tom Warren wrote:
> A comparison of registers between our internal NV U-Boot and
> u-boot-tegra/next showed some discrepancies in the MSELECT
> clock divisor programming. T20 doesn't have a MSELECT clk src reg.
I'm not familiar with this code/HW, but it seems OK at a quick glance, so,
Reviewed-by: Stephen Warren <swarren@nvidia.com>
prev parent reply other threads:[~2013-04-03 23:28 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-03 23:17 [U-Boot] [PATCH] Tegra: Fix MSELECT clock divisors for T30/T114 Tom Warren
2013-04-03 23:28 ` Stephen Warren [this message]
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