From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: Re: [PATCH 1/4] xen/arm: basic PSCI support, implement cpu_on Date: Tue, 09 Apr 2013 15:23:51 +0100 Message-ID: <51642477.5050503@arm.com> References: <1363891353-13827-1-git-send-email-stefano.stabellini@eu.citrix.com> <1365515874.10725.33.camel@zakaz.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1365515874.10725.33.camel@zakaz.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: Will Deacon , "xen-devel@lists.xensource.com" , "Tim (Xen.org)" , Stefano Stabellini List-Id: xen-devel@lists.xenproject.org On 09/04/13 14:57, Ian Campbell wrote: > On Thu, 2013-03-21 at 18:42 +0000, Stefano Stabellini wrote: >> Implement support for ARM Power State Coordination Interface, PSCI in >> short. The current implementation is based on HVC and only supports the >> cpu_on call. > > Doesn't the PSCI interface require the use of SMC not HVC? You can use both, and KVM uses HVC. > I thought I heard Charles say at connect that there was now a PSCI v2, > and I suspect I'm looking at the v1 document (which mentions HVC only in > passing). Which interface did you implement? > > Anyhow, we can trap SMCs to the hypervisor by setting the right control > register bits. We should do this anyway -- no good can come of a guest > making a call direct to the monitor! Trapping guest access to Secure mode is always a good idea! ;-) Unfortunately, there's a catch on ARMv8. If the CPU doesn't implement secure mode, then SMC will UNDEF at the current exception level (not trapping to EL2). Which means that for ARMv8, you basically have to mandate HVC for PSCI at the HYP level... M. -- Jazz is not dead. It just smells funny...