From mboxrd@z Thu Jan 1 00:00:00 1970 Reply-To: kernel-hardening@lists.openwall.com Message-ID: <516597DB.4020208@zytor.com> Date: Wed, 10 Apr 2013 09:48:27 -0700 From: "H. Peter Anvin" MIME-Version: 1.0 References: <20130408224328.GA17641@www.outflux.net> <51634935.9010905@zytor.com> <877gkc596d.fsf@xmission.com> <20130410095716.GF24443@gmail.com> <87sj2yzn1a.fsf@xmission.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: [kernel-hardening] Re: [PATCH] x86: make IDT read-only To: Eric Northup Cc: "Eric W. Biederman" , Ingo Molnar , Kees Cook , Ingo Molnar , Linux Kernel Mailing List , Thomas Gleixner , the arch/x86 maintainers , Konrad Rzeszutek Wilk , Jeremy Fitzhardinge , Marcelo Tosatti , Alex Shi , Borislav Petkov , Alexander Duyck , Frederic Weisbecker , Steven Rostedt , "Paul E. McKenney" , Xen Devel , lf-virt , "kernel-hardening@lists.openwall.com" , Dan Rosenberg , Julien Tinnes , Will Drewry List-ID: On 04/10/2013 09:31 AM, Eric Northup wrote: >> >> If the effect is measurable I agree it is a legitimate optimization. At >> one point there was a suggestion to make the code in the IDT vectors >> differ based on the which interrupt was registed. While that can also >> reduce cache misses that can get hairy very quickly, and of course that >> would require read-write IDTs. > > read-write IDT or GDT are fine: map them twice, once read+write, once > read-only. Point the GDTR and IDTR at the read-only alias. > Well, it is weaker, because if you can discover the pointer to the writable alias you win. Now, as has been pointed out the GDT needs to be writable on 32 bits as a matter of hardware requirement. However, doing it for 64 bits only is probably enough of a win. -hpa From mboxrd@z Thu Jan 1 00:00:00 1970 From: "H. Peter Anvin" Subject: Re: [PATCH] x86: make IDT read-only Date: Wed, 10 Apr 2013 09:48:27 -0700 Message-ID: <516597DB.4020208@zytor.com> References: <20130408224328.GA17641@www.outflux.net> <51634935.9010905@zytor.com> <877gkc596d.fsf@xmission.com> <20130410095716.GF24443@gmail.com> <87sj2yzn1a.fsf@xmission.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: virtualization-bounces@lists.linux-foundation.org Errors-To: virtualization-bounces@lists.linux-foundation.org To: Eric Northup Cc: Jeremy Fitzhardinge , "kernel-hardening@lists.openwall.com" , Frederic Weisbecker , Dan Rosenberg , lf-virt , Ingo Molnar , Alex Shi , the arch/x86 maintainers , Ingo Molnar , "Paul E. McKenney" , Alexander Duyck , Kees Cook , Julien Tinnes , Konrad Rzeszutek Wilk , Borislav Petkov , Steven Rostedt , Xen Devel , Thomas Gleixner , Will Drewry , Linux Kernel Mailing List , "Eric W. Biederman" List-Id: virtualization@lists.linuxfoundation.org On 04/10/2013 09:31 AM, Eric Northup wrote: >> >> If the effect is measurable I agree it is a legitimate optimization. At >> one point there was a suggestion to make the code in the IDT vectors >> differ based on the which interrupt was registed. While that can also >> reduce cache misses that can get hairy very quickly, and of course that >> would require read-write IDTs. > > read-write IDT or GDT are fine: map them twice, once read+write, once > read-only. Point the GDTR and IDTR at the read-only alias. > Well, it is weaker, because if you can discover the pointer to the writable alias you win. Now, as has been pointed out the GDT needs to be writable on 32 bits as a matter of hardware requirement. However, doing it for 64 bits only is probably enough of a win. -hpa From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937164Ab3DJQum (ORCPT ); Wed, 10 Apr 2013 12:50:42 -0400 Received: from terminus.zytor.com ([198.137.202.10]:32794 "EHLO mail.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937125Ab3DJQul (ORCPT ); Wed, 10 Apr 2013 12:50:41 -0400 Message-ID: <516597DB.4020208@zytor.com> Date: Wed, 10 Apr 2013 09:48:27 -0700 From: "H. Peter Anvin" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130311 Thunderbird/17.0.4 MIME-Version: 1.0 To: Eric Northup CC: "Eric W. Biederman" , Ingo Molnar , Kees Cook , Ingo Molnar , Linux Kernel Mailing List , Thomas Gleixner , the arch/x86 maintainers , Konrad Rzeszutek Wilk , Jeremy Fitzhardinge , Marcelo Tosatti , Alex Shi , Borislav Petkov , Alexander Duyck , Frederic Weisbecker , Steven Rostedt , "Paul E. McKenney" , Xen Devel , lf-virt , "kernel-hardening@lists.openwall.com" , Dan Rosenberg , Julien Tinnes , Will Drewry Subject: Re: [PATCH] x86: make IDT read-only References: <20130408224328.GA17641@www.outflux.net> <51634935.9010905@zytor.com> <877gkc596d.fsf@xmission.com> <20130410095716.GF24443@gmail.com> <87sj2yzn1a.fsf@xmission.com> In-Reply-To: X-Enigmail-Version: 1.5.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/10/2013 09:31 AM, Eric Northup wrote: >> >> If the effect is measurable I agree it is a legitimate optimization. At >> one point there was a suggestion to make the code in the IDT vectors >> differ based on the which interrupt was registed. While that can also >> reduce cache misses that can get hairy very quickly, and of course that >> would require read-write IDTs. > > read-write IDT or GDT are fine: map them twice, once read+write, once > read-only. Point the GDTR and IDTR at the read-only alias. > Well, it is weaker, because if you can discover the pointer to the writable alias you win. Now, as has been pointed out the GDT needs to be writable on 32 bits as a matter of hardware requirement. However, doing it for 64 bits only is probably enough of a win. -hpa