From: Suravee Suthikulanit <suravee.suthikulpanit@amd.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: Jacob Shin <jacob.shin@amd.com>,
xiantao.zhang@intel.com, xen-devel <xen-devel@lists.xen.org>
Subject: Re: [PATCH v3 0/3] x86/IOMMU: multi-vector MSI prerequisites
Date: Mon, 15 Apr 2013 11:14:50 -0500 [thread overview]
Message-ID: <516C277A.8030308@amd.com> (raw)
In-Reply-To: <516C2E2A02000078000CD423@nat28.tlf.novell.com>
On 4/15/2013 9:43 AM, Jan Beulich wrote:
>>>> On 13.04.13 at 03:16, Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> wrote:
>> On 4/12/2013 5:18 AM, Jan Beulich wrote:
>>> 1: IOMMU: allow MSI message to IRTE propagation to fail
>>> 2: AMD IOMMU: allocate IRTE entries instead of using a static mapping
>>> 3: AMD IOMMU: untie remap and vector maps
>>>
>>> See the individual patches for what, if anything, has changed from v2.
>>>
>>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>> This patch setfix the previous issue we sawfrom the get_intremap_entry()
>> causing the ASSERT on (table != NULL). Now the system is booting.
>>
>> However, I think there are some issues with the interrupt remapping for
>> the USBdevices. During dom0 booting, it gave error w/ regarding timeout
>> during loadingsome USB drivers. Also, lsmodis showing "hid_generic"
>> module is missing. This resulting in the USBmouse and keyboard are not
>> working.
> So I would guess something must be wrong with the IO-APIC
> related code paths then.
Why is this IO-APIC and not MSI or MSIx?
> I just went through them again, but the
> only thing I spotted was a pointless duplicate assignment to
> ioapic_sbdf[].pin_2_idx[] in amd_iommu_setup_ioapic_remapping().
> Sadly we don't have the 'V' debug key for AMD yet, otherwise the
> combination of 'V' and 'z' output would likely tell us quite clearly
> what's wrong. Looking at 'z' might still be worthwhile though...
>
> Jan
>
> Jan
>
>
On another topic, in arch/x86/msi.c, in the function
"setup_msi_affinity()", the code does:
1. "read_msi_msg"
2. Modify the affitity mask
3. "write_msi_msg" back the register value.
In read, if the interrupt remapping is enabled, from the patch, the
function returns the MSI data with remapped information from IOMMU. Then
in write, if the interrupt remapping is enabled, the function will
update the IOMMU interrupt remapping entries with the already "remapped"
vector. In this case, you would be updating the incorrect IOMMU IRTE.
Suravee
next prev parent reply other threads:[~2013-04-15 16:14 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-12 10:18 [PATCH v3 0/3] x86/IOMMU: multi-vector MSI prerequisites Jan Beulich
2013-04-12 10:22 ` [PATCH v3 1/3] IOMMU: allow MSI message to IRTE propagation to fail Jan Beulich
2013-04-15 6:38 ` Zhang, Xiantao
2013-04-12 10:23 ` [PATCH v3 2/3] AMD IOMMU: allocate IRTE entries instead of using a static mapping Jan Beulich
2013-04-12 10:23 ` [PATCH v3 3/3] AMD IOMMU: untie remap and vector maps Jan Beulich
2013-04-13 1:16 ` [PATCH v3 0/3] x86/IOMMU: multi-vector MSI prerequisites Suravee Suthikulpanit
2013-04-15 14:43 ` Jan Beulich
2013-04-15 16:14 ` Suravee Suthikulanit [this message]
2013-04-16 6:43 ` Jan Beulich
2013-04-18 17:25 ` Suravee Suthikulanit
2013-04-19 7:29 ` Jan Beulich
2013-04-22 23:58 ` Suravee Suthikulanit
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