Re: [PATCH resend 2/2] clk: tegra: add ac97 controller clock

[Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]

On Monday 15 April 2013 01:01 PM, Lucas Stach wrote:
> AC97 controller clock is hardwired to pll_a_out0.
>
> Signed-off-by: Lucas Stach <dev-8ppwABl0HbeELgA04lAiVw@public.gmane.org>
> ---

It was not there in previous implementation neither do we implement it 
in our downstream kernel.

Lucas, are you using this clock anywhere?

Reviewed-by: Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

>   drivers/clk/tegra/clk-tegra20.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
> index a73278f..bbcca91 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -897,6 +897,14 @@ static void __init tegra20_periph_clk_init(void)
>   	struct clk *clk;
>   	int i;
>   
> +	/* ac97 */
> +	clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
> +				    TEGRA_PERIPH_ON_APB,
> +				    clk_base, 0, 3, &periph_l_regs,
> +				    periph_clk_enb_refcnt);
> +	clk_register_clkdev(clk, NULL, "tegra20-ac97");
> +	clks[ac97] = clk;
> +
>   	/* apbdma */
>   	clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
>   				    0, 34, &periph_h_regs,