[PATCH 1/5] clk: exynos4: Add additional G2D clocks

[PATCH 1/5] clk: exynos4: Add additional G2D clocks

[Sachin Kamat]

Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D
IP.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Mike Turquette <mturquette@linaro.org>
---
 .../devicetree/bindings/clock/exynos4-clock.txt    |    3 ++-
 drivers/clk/samsung/clk-exynos4.c                  |    9 +++++++--
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index ea5e26f..14d5c2a 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -102,6 +102,7 @@ Exynos4 SoC and this is specified where applicable.
   sclk_spi0_isp       174     Exynos4x12
   sclk_spi1_isp       175     Exynos4x12
   sclk_uart_isp       176     Exynos4x12
+  sclk_fimg2d         177
 
 	      [Peripheral Clock Gates]
 
@@ -129,7 +130,7 @@ Exynos4 SoC and this is specified where applicable.
   smmu_mfcl           274
   smmu_mfcr           275
   g3d                 276
-  g2d                 277     Exynos4210
+  g2d                 277
   rotator             278     Exynos4210
   mdma                279     Exynos4210
   smmu_g2d            280     Exynos4210
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 26f2a85..09cf161 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -152,7 +152,7 @@ enum exynos4_clks {
 	sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
 	sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
 	sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
-	sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp,
+	sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d,
 
 	/* gate clocks */
 	fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
@@ -487,6 +487,9 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
 	MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
 	MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
 	MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
+	MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
+	MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
+	MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
 };
 
 /* list of divider clocks supported in all exynos4 soc's */
@@ -555,7 +558,7 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
 /* list of divider clocks supported in exynos4210 soc */
 static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
 	DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
-	DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
+	DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
 	DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
 	DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
 	DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
@@ -585,6 +588,7 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
 	DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
 	DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
 	DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
+	DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
 };
 
 /* list of gate clocks supported in all exynos4 soc's */
@@ -910,6 +914,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
 			CLK_IGNORE_UNUSED, 0),
 	GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
 			CLK_IGNORE_UNUSED, 0),
+	GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
 };
 
 #ifdef CONFIG_OF
-- 
1.7.9.5

[PATCH 2/5] ARM: dts: Remove duplicate and add missing G2D nodes

[Sachin Kamat]

G2D node got added twice in exynos4412-smdk4412.dts instead of
getting added to exynos4412-origen.dts. Remove the duplicate entry
and add it to exynos4412-origen.dts.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
---
 arch/arm/boot/dts/exynos4412-origen.dts   |    4 ++++
 arch/arm/boot/dts/exynos4412-smdk4412.dts |    4 ----
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 790a999..ca73c42 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -98,6 +98,10 @@
 		};
 	};
 
+	g2d@10800000 {
+		status = "okay";
+	};
+
 	sdhci@12530000 {
 		bus-width = <4>;
 		pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index c52b01f..a8ba195 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -31,10 +31,6 @@
 		status = "okay";
 	};
 
-	g2d@10800000 {
-		status = "okay";
-	};
-
 	pinctrl@11000000 {
 		keypad_rows: keypad-rows {
 			samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
-- 
1.7.9.5

[PATCH 3/5] ARM: dts: Add clock entries to G2D node for exynos4210

[Sachin Kamat]

Added clock entries to G2D node.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
---
 arch/arm/boot/dts/exynos4210.dtsi |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 66e6b03..50ab9d4 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -117,6 +117,8 @@
 		compatible = "samsung,s5pv210-g2d";
 		reg = <0x12800000 0x1000>;
 		interrupts = <0 89 0>;
+		clocks = <&clock 177>, <&clock 277>;
+		clock-names = "sclk_fimg2d", "fimg2d";
 		status = "disabled";
 	};
 };
-- 
1.7.9.5

[PATCH 4/5] ARM: dts: Add clock entries to G2D node for exynos4x12

[Sachin Kamat]

Added clock entries to G2D node for exynos4x12 DT file.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
---
 arch/arm/boot/dts/exynos4x12.dtsi |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index e3380a7..284abc6 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -77,6 +77,8 @@
 		compatible = "samsung,exynos4212-g2d";
 		reg = <0x10800000 0x1000>;
 		interrupts = <0 89 0>;
+		clocks = <&clock 177>, <&clock 277>;
+		clock-names = "sclk_fimg2d", "fimg2d";
 		status = "disabled";
 	};
 };
-- 
1.7.9.5

[PATCH 5/5] ARM: dts: Update G2D documentation for clock entries

[Sachin Kamat]

Added clock entry definitions to G2D bindings document.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Cc: devicetree-discuss@lists.ozlabs.org
---
 .../devicetree/bindings/gpu/samsung-g2d.txt        |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
index 2b14a94..3f454ff 100644
--- a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
+++ b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
@@ -10,11 +10,16 @@ Required properties:
 	  mapped region.
 
   - interrupts : G2D interrupt number to the CPU.
+  - clocks : from common clock binding: handle to G2D clocks.
+  - clock-names : from common clock binding: must contain "sclk_fimg2d" and
+		  "fimg2d", corresponding to entries in the clocks property.
 
 Example:
 	g2d@12800000 {
 		compatible = "samsung,s5pv210-g2d";
 		reg = <0x12800000 0x1000>;
 		interrupts = <0 89 0>;
+		clocks = <&clock 177>, <&clock 277>;
+		clock-names = "sclk_fimg2d", "fimg2d";
 		status = "disabled";
 	};
-- 
1.7.9.5

Re: [PATCH 3/5] ARM: dts: Add clock entries to G2D node for exynos4210

[Sylwester Nawrocki]

Hi Sachin,

On 04/18/2013 01:15 PM, Sachin Kamat wrote:
> Added clock entries to G2D node.
> 
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
>  arch/arm/boot/dts/exynos4210.dtsi |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
> index 66e6b03..50ab9d4 100644
> --- a/arch/arm/boot/dts/exynos4210.dtsi
> +++ b/arch/arm/boot/dts/exynos4210.dtsi
> @@ -117,6 +117,8 @@
>  		compatible = "samsung,s5pv210-g2d";
>  		reg = <0x12800000 0x1000>;
>  		interrupts = <0 89 0>;
> +		clocks = <&clock 177>, <&clock 277>;
> +		clock-names = "sclk_fimg2d", "fimg2d";

Same clocks are used for exynos4210 and exynos4212/4412. Wouldn't
it work if you have added those properties to exynos4.dtsi, instead
of having same entries in exynos4210.dtsi and exynos4x12.dtsi  ?

Thanks,
Sylwester

Re: [PATCH 3/5] ARM: dts: Add clock entries to G2D node for exynos4210

[Sachin Kamat]

Hi Sylwester,

On 18 April 2013 17:08, Sylwester Nawrocki <s.nawrocki@samsung.com> wrote:
> Hi Sachin,
>
> On 04/18/2013 01:15 PM, Sachin Kamat wrote:
>> Added clock entries to G2D node.
>>
>> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
>> ---
>>  arch/arm/boot/dts/exynos4210.dtsi |    2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
>> index 66e6b03..50ab9d4 100644
>> --- a/arch/arm/boot/dts/exynos4210.dtsi
>> +++ b/arch/arm/boot/dts/exynos4210.dtsi
>> @@ -117,6 +117,8 @@
>>               compatible = "samsung,s5pv210-g2d";
>>               reg = <0x12800000 0x1000>;
>>               interrupts = <0 89 0>;
>> +             clocks = <&clock 177>, <&clock 277>;
>> +             clock-names = "sclk_fimg2d", "fimg2d";
>
> Same clocks are used for exynos4210 and exynos4212/4412. Wouldn't
> it work if you have added those properties to exynos4.dtsi, instead
> of having same entries in exynos4210.dtsi and exynos4x12.dtsi  ?

The clocks are the same. However, base address of register is
different for 4210 and 4x12.
That was the reason 2 separate nodes were created. Do you want me to
create a common node in exynos4.dtsi with all the common properties
and separate nodes in exynos4210.dtsi and exynos4x12.dtsi with just
the 'reg' property?


-- 
With warm regards,
Sachin

Re: [PATCH 3/5] ARM: dts: Add clock entries to G2D node for exynos4210

[Sylwester Nawrocki]

On 04/18/2013 01:54 PM, Sachin Kamat wrote:
>>> diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
>>> index 66e6b03..50ab9d4 100644
>>> --- a/arch/arm/boot/dts/exynos4210.dtsi
>>> +++ b/arch/arm/boot/dts/exynos4210.dtsi
>>> @@ -117,6 +117,8 @@
>>>               compatible = "samsung,s5pv210-g2d";
>>>               reg = <0x12800000 0x1000>;
>>>               interrupts = <0 89 0>;
>>> +             clocks = <&clock 177>, <&clock 277>;
>>> +             clock-names = "sclk_fimg2d", "fimg2d";
>>
>> Same clocks are used for exynos4210 and exynos4212/4412. Wouldn't
>> it work if you have added those properties to exynos4.dtsi, instead
>> of having same entries in exynos4210.dtsi and exynos4x12.dtsi  ?
> 
> The clocks are the same. However, base address of register is
> different for 4210 and 4x12.
> That was the reason 2 separate nodes were created. Do you want me to
> create a common node in exynos4.dtsi with all the common properties
> and separate nodes in exynos4210.dtsi and exynos4x12.dtsi with just
> the 'reg' property?

Ah, ok then. I'm fine either way. The compatible strings are also
different so it's probably better to leave exynos4.dtsi out and
have full nodes listed in both exynos4210/4x12.dtsi.

Thanks,
Sylwester

Re: [PATCH 3/5] ARM: dts: Add clock entries to G2D node for exynos4210

[Sachin Kamat]

On 18 April 2013 18:57, Sylwester Nawrocki <s.nawrocki@samsung.com> wrote:
> On 04/18/2013 01:54 PM, Sachin Kamat wrote:
>>>> diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
>>>> index 66e6b03..50ab9d4 100644
>>>> --- a/arch/arm/boot/dts/exynos4210.dtsi
>>>> +++ b/arch/arm/boot/dts/exynos4210.dtsi
>>>> @@ -117,6 +117,8 @@
>>>>               compatible = "samsung,s5pv210-g2d";
>>>>               reg = <0x12800000 0x1000>;
>>>>               interrupts = <0 89 0>;
>>>> +             clocks = <&clock 177>, <&clock 277>;
>>>> +             clock-names = "sclk_fimg2d", "fimg2d";
>>>
>>> Same clocks are used for exynos4210 and exynos4212/4412. Wouldn't
>>> it work if you have added those properties to exynos4.dtsi, instead
>>> of having same entries in exynos4210.dtsi and exynos4x12.dtsi  ?
>>
>> The clocks are the same. However, base address of register is
>> different for 4210 and 4x12.
>> That was the reason 2 separate nodes were created. Do you want me to
>> create a common node in exynos4.dtsi with all the common properties
>> and separate nodes in exynos4210.dtsi and exynos4x12.dtsi with just
>> the 'reg' property?
>
> Ah, ok then. I'm fine either way. The compatible strings are also
> different so it's probably better to leave exynos4.dtsi out and
> have full nodes listed in both exynos4210/4x12.dtsi.

Yes. I will leave it the way it is.


-- 
With warm regards,
Sachin

Re: [PATCH 1/5] clk: exynos4: Add additional G2D clocks

[Mike Turquette]

Quoting Sachin Kamat (2013-04-18 04:15:15)
> Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D
> IP.
> 
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> Cc: Thomas Abraham <thomas.abraham@linaro.org>
> Cc: Mike Turquette <mturquette@linaro.org>

Acked-by: Mike Turquette <mturquette@linaro.org>

> ---
>  .../devicetree/bindings/clock/exynos4-clock.txt    |    3 ++-
>  drivers/clk/samsung/clk-exynos4.c                  |    9 +++++++--
>  2 files changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
> index ea5e26f..14d5c2a 100644
> --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
> @@ -102,6 +102,7 @@ Exynos4 SoC and this is specified where applicable.
>    sclk_spi0_isp       174     Exynos4x12
>    sclk_spi1_isp       175     Exynos4x12
>    sclk_uart_isp       176     Exynos4x12
> +  sclk_fimg2d         177
>  
>               [Peripheral Clock Gates]
>  
> @@ -129,7 +130,7 @@ Exynos4 SoC and this is specified where applicable.
>    smmu_mfcl           274
>    smmu_mfcr           275
>    g3d                 276
> -  g2d                 277     Exynos4210
> +  g2d                 277
>    rotator             278     Exynos4210
>    mdma                279     Exynos4210
>    smmu_g2d            280     Exynos4210
> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
> index 26f2a85..09cf161 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -152,7 +152,7 @@ enum exynos4_clks {
>         sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
>         sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
>         sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
> -       sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp,
> +       sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d,
>  
>         /* gate clocks */
>         fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
> @@ -487,6 +487,9 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
>         MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
>         MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
>         MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
> +       MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
> +       MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
> +       MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
>  };
>  
>  /* list of divider clocks supported in all exynos4 soc's */
> @@ -555,7 +558,7 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
>  /* list of divider clocks supported in exynos4210 soc */
>  static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
>         DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
> -       DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
> +       DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
>         DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
>         DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
>         DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
> @@ -585,6 +588,7 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
>         DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
>         DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
>         DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
> +       DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
>  };
>  
>  /* list of gate clocks supported in all exynos4 soc's */
> @@ -910,6 +914,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
>                         CLK_IGNORE_UNUSED, 0),
>         GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
>                         CLK_IGNORE_UNUSED, 0),
> +       GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
>  };
>  
>  #ifdef CONFIG_OF
> -- 
> 1.7.9.5

Re: [PATCH 1/5] clk: exynos4: Add additional G2D clocks

[Sachin Kamat]

On 18 April 2013 22:29, Mike Turquette <mturquette@linaro.org> wrote:
> Quoting Sachin Kamat (2013-04-18 04:15:15)
>> Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D
>> IP.
>>
>> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
>> Cc: Thomas Abraham <thomas.abraham@linaro.org>
>> Cc: Mike Turquette <mturquette@linaro.org>
>
> Acked-by: Mike Turquette <mturquette@linaro.org>

Ping Kukjin.

-- 
With warm regards,
Sachin

Re: [PATCH 1/5] clk: exynos4: Add additional G2D clocks

[Sachin Kamat]

Hi Kukjin,

Can you please apply this series pending since a long time.


On 18 April 2013 22:29, Mike Turquette <mturquette@linaro.org> wrote:
> Quoting Sachin Kamat (2013-04-18 04:15:15)
>> Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D
>> IP.
>>
>> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
>> Cc: Thomas Abraham <thomas.abraham@linaro.org>
>> Cc: Mike Turquette <mturquette@linaro.org>
>
> Acked-by: Mike Turquette <mturquette@linaro.org>
>
>> ---
>>  .../devicetree/bindings/clock/exynos4-clock.txt    |    3 ++-
>>  drivers/clk/samsung/clk-exynos4.c                  |    9 +++++++--
>>  2 files changed, 9 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
>> index ea5e26f..14d5c2a 100644
>> --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
>> +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
>> @@ -102,6 +102,7 @@ Exynos4 SoC and this is specified where applicable.
>>    sclk_spi0_isp       174     Exynos4x12
>>    sclk_spi1_isp       175     Exynos4x12
>>    sclk_uart_isp       176     Exynos4x12
>> +  sclk_fimg2d         177
>>
>>               [Peripheral Clock Gates]
>>
>> @@ -129,7 +130,7 @@ Exynos4 SoC and this is specified where applicable.
>>    smmu_mfcl           274
>>    smmu_mfcr           275
>>    g3d                 276
>> -  g2d                 277     Exynos4210
>> +  g2d                 277
>>    rotator             278     Exynos4210
>>    mdma                279     Exynos4210
>>    smmu_g2d            280     Exynos4210
>> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
>> index 26f2a85..09cf161 100644
>> --- a/drivers/clk/samsung/clk-exynos4.c
>> +++ b/drivers/clk/samsung/clk-exynos4.c
>> @@ -152,7 +152,7 @@ enum exynos4_clks {
>>         sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
>>         sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
>>         sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
>> -       sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp,
>> +       sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d,
>>
>>         /* gate clocks */
>>         fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
>> @@ -487,6 +487,9 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
>>         MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
>>         MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
>>         MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
>> +       MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
>> +       MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
>> +       MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
>>  };
>>
>>  /* list of divider clocks supported in all exynos4 soc's */
>> @@ -555,7 +558,7 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
>>  /* list of divider clocks supported in exynos4210 soc */
>>  static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
>>         DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
>> -       DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
>> +       DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
>>         DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
>>         DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
>>         DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
>> @@ -585,6 +588,7 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
>>         DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
>>         DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
>>         DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
>> +       DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
>>  };
>>
>>  /* list of gate clocks supported in all exynos4 soc's */
>> @@ -910,6 +914,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
>>                         CLK_IGNORE_UNUSED, 0),
>>         GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
>>                         CLK_IGNORE_UNUSED, 0),
>> +       GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
>>  };
>>
>>  #ifdef CONFIG_OF
>> --
>> 1.7.9.5



-- 
With warm regards,
Sachin

Re: [PATCH 1/5] clk: exynos4: Add additional G2D clocks

[Sachin Kamat]

Ping on this series..

On 18 April 2013 22:29, Mike Turquette <mturquette@linaro.org> wrote:
> Quoting Sachin Kamat (2013-04-18 04:15:15)
>> Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D
>> IP.
>>
>> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
>> Cc: Thomas Abraham <thomas.abraham@linaro.org>
>> Cc: Mike Turquette <mturquette@linaro.org>
>
> Acked-by: Mike Turquette <mturquette@linaro.org>
>
>> ---
>>  .../devicetree/bindings/clock/exynos4-clock.txt    |    3 ++-
>>  drivers/clk/samsung/clk-exynos4.c                  |    9 +++++++--
>>  2 files changed, 9 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
>> index ea5e26f..14d5c2a 100644
>> --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
>> +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
>> @@ -102,6 +102,7 @@ Exynos4 SoC and this is specified where applicable.
>>    sclk_spi0_isp       174     Exynos4x12
>>    sclk_spi1_isp       175     Exynos4x12
>>    sclk_uart_isp       176     Exynos4x12
>> +  sclk_fimg2d         177
>>
>>               [Peripheral Clock Gates]
>>
>> @@ -129,7 +130,7 @@ Exynos4 SoC and this is specified where applicable.
>>    smmu_mfcl           274
>>    smmu_mfcr           275
>>    g3d                 276
>> -  g2d                 277     Exynos4210
>> +  g2d                 277
>>    rotator             278     Exynos4210
>>    mdma                279     Exynos4210
>>    smmu_g2d            280     Exynos4210
>> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
>> index 26f2a85..09cf161 100644
>> --- a/drivers/clk/samsung/clk-exynos4.c
>> +++ b/drivers/clk/samsung/clk-exynos4.c
>> @@ -152,7 +152,7 @@ enum exynos4_clks {
>>         sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
>>         sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
>>         sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
>> -       sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp,
>> +       sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d,
>>
>>         /* gate clocks */
>>         fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
>> @@ -487,6 +487,9 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
>>         MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
>>         MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
>>         MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
>> +       MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
>> +       MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
>> +       MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
>>  };
>>
>>  /* list of divider clocks supported in all exynos4 soc's */
>> @@ -555,7 +558,7 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
>>  /* list of divider clocks supported in exynos4210 soc */
>>  static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
>>         DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
>> -       DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
>> +       DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
>>         DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
>>         DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
>>         DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
>> @@ -585,6 +588,7 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
>>         DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
>>         DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
>>         DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
>> +       DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
>>  };
>>
>>  /* list of gate clocks supported in all exynos4 soc's */
>> @@ -910,6 +914,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
>>                         CLK_IGNORE_UNUSED, 0),
>>         GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
>>                         CLK_IGNORE_UNUSED, 0),
>> +       GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
>>  };
>>
>>  #ifdef CONFIG_OF
>> --
>> 1.7.9.5



-- 
With warm regards,
Sachin

RE: [PATCH 1/5] clk: exynos4: Add additional G2D clocks

[Kukjin Kim]

Mike Turquette wrote:
> 
> Quoting Sachin Kamat (2013-04-18 04:15:15)
> > Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D
> > IP.
> >
> > Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> > Cc: Thomas Abraham <thomas.abraham@linaro.org>
> > Cc: Mike Turquette <mturquette@linaro.org>
> 
> Acked-by: Mike Turquette <mturquette@linaro.org>
> 
Mike, do you want me to take this one with others into samsung tree?

- Kukjin

> > ---
> >  .../devicetree/bindings/clock/exynos4-clock.txt    |    3 ++-
> >  drivers/clk/samsung/clk-exynos4.c                  |    9 +++++++--
> >  2 files changed, 9 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
> b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
> > index ea5e26f..14d5c2a 100644
> > --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
> > +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
> > @@ -102,6 +102,7 @@ Exynos4 SoC and this is specified where applicable.
> >    sclk_spi0_isp       174     Exynos4x12
> >    sclk_spi1_isp       175     Exynos4x12
> >    sclk_uart_isp       176     Exynos4x12
> > +  sclk_fimg2d         177
> >
> >               [Peripheral Clock Gates]
> >
> > @@ -129,7 +130,7 @@ Exynos4 SoC and this is specified where applicable.
> >    smmu_mfcl           274
> >    smmu_mfcr           275
> >    g3d                 276
> > -  g2d                 277     Exynos4210
> > +  g2d                 277
> >    rotator             278     Exynos4210
> >    mdma                279     Exynos4210
> >    smmu_g2d            280     Exynos4210
> > diff --git a/drivers/clk/samsung/clk-exynos4.c
> b/drivers/clk/samsung/clk-exynos4.c
> > index 26f2a85..09cf161 100644
> > --- a/drivers/clk/samsung/clk-exynos4.c
> > +++ b/drivers/clk/samsung/clk-exynos4.c
> > @@ -152,7 +152,7 @@ enum exynos4_clks {
> >         sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1,
> sclk_spi2,
> >         sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2,
> sclk_i2s1,
> >         sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d,
> sclk_pwm_isp,
> > -       sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp,
> > +       sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d,
> >
> >         /* gate clocks */
> >         fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
> > @@ -487,6 +487,9 @@ static struct samsung_mux_clock exynos4x12_mux_clks[]
> __initdata = {
> >         MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
> >         MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
> >         MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
> > +       MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
> > +       MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
> > +       MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
> >  };
> >
> >  /* list of divider clocks supported in all exynos4 soc's */
> > @@ -555,7 +558,7 @@ static struct samsung_div_clock exynos4_div_clks[]
> __initdata = {
> >  /* list of divider clocks supported in exynos4210 soc */
> >  static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
> >         DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
> > -       DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
> > +       DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
> >         DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
> >         DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
> >         DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
> > @@ -585,6 +588,7 @@ static struct samsung_div_clock exynos4x12_div_clks[]
> __initdata = {
> >         DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
> >         DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1,
> 4, 3),
> >         DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8,
> 3),
> > +       DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
> >  };
> >
> >  /* list of gate clocks supported in all exynos4 soc's */
> > @@ -910,6 +914,7 @@ static struct samsung_gate_clock
> exynos4x12_gate_clks[] __initdata = {
> >                         CLK_IGNORE_UNUSED, 0),
> >         GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
> >                         CLK_IGNORE_UNUSED, 0),
> > +       GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
> >  };
> >
> >  #ifdef CONFIG_OF
> > --
> > 1.7.9.5

RE: [PATCH 2/5] ARM: dts: Remove duplicate and add missing G2D nodes

[Kukjin Kim]

Sachin Kamat wrote:
> 
> G2D node got added twice in exynos4412-smdk4412.dts instead of
> getting added to exynos4412-origen.dts. Remove the duplicate entry
> and add it to exynos4412-origen.dts.
> 
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
>  arch/arm/boot/dts/exynos4412-origen.dts   |    4 ++++
>  arch/arm/boot/dts/exynos4412-smdk4412.dts |    4 ----
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
> b/arch/arm/boot/dts/exynos4412-origen.dts
> index 790a999..ca73c42 100644
> --- a/arch/arm/boot/dts/exynos4412-origen.dts
> +++ b/arch/arm/boot/dts/exynos4412-origen.dts
> @@ -98,6 +98,10 @@
>  		};
>  	};
> 
> +	g2d@10800000 {
> +		status = "okay";
> +	};
> +
>  	sdhci@12530000 {
>  		bus-width = <4>;
>  		pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
> diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts
> b/arch/arm/boot/dts/exynos4412-smdk4412.dts
> index c52b01f..a8ba195 100644
> --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
> +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
> @@ -31,10 +31,6 @@
>  		status = "okay";
>  	};
> 
> -	g2d@10800000 {
> -		status = "okay";
> -	};
> -
>  	pinctrl@11000000 {
>  		keypad_rows: keypad-rows {
>  			samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
> --
> 1.7.9.5

Ooops :(

The 2 to 5 patches look good to me.

Applied, btw, please make a cover 0/5 for series next time.

Thanks.

- Kukjin

RE: [PATCH 1/5] clk: exynos4: Add additional G2D clocks

[Kukjin Kim]

Kukjin Kim wrote:
> 
> Mike Turquette wrote:
> >
> > Quoting Sachin Kamat (2013-04-18 04:15:15)
> > > Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D
> > > IP.
> > >
> > > Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> > > Cc: Thomas Abraham <thomas.abraham@linaro.org>
> > > Cc: Mike Turquette <mturquette@linaro.org>
> >
> > Acked-by: Mike Turquette <mturquette@linaro.org>
> >
> Mike, do you want me to take this one with others into samsung tree?
> 
I applied this into samsung tree.

- Kukjin