From mboxrd@z Thu Jan  1 00:00:00 1970
From: =?ISO-8859-1?Q?Christian_K=F6nig?= <deathsimple@vodafone.de>
Subject: Re: drm/radeon: add radeon_atom_get_clock_dividers helper
Date: Fri, 19 Apr 2013 17:45:32 +0200
Message-ID: <5171669C.1010601@vodafone.de>
References: <20130418184709.GA11596@elgon.mountain>
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To: Dan Carpenter <dan.carpenter@oracle.com>, Alex Deucher <alexdeucher@gmail.com>
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Am 18.04.2013 20:47, schrieb Dan Carpenter:
> Hello Christian K=F6nig,
>
> The patch 7062ab67d4c6: "drm/radeon: add
> radeon_atom_get_clock_dividers helper" from Apr 8, 2013, has endian
> bugs.
>
> drivers/gpu/drm/radeon/radeon_atombios.c
>    2712                          if (clock_type =3D=3D COMPUTE_ENGINE_PLL=
_PARAM) {
>    2713                                  args.v3.ulClock.ulComputeClockFl=
ag =3D clock_type;
>    2714                                  args.v3.ulClock.ulClockFreq =3D =
cpu_to_le32(clock);       /* 10 khz */
>                                                          ^^^^^^^^^^^
> This is 24 bit bitfield so it can't store a __le32.  On little endian
> systems it will truncate high bits away so that's ok, but on big endian
> it will break.
>
>    2715
>    2716                                  atom_execute_table(rdev->mode_in=
fo.atom_context, index, (uint32_t *)&args);
>    2717
>    2718                                  dividers->post_div =3D args.v3.u=
cPostDiv;
>    2719                                  dividers->enable_post_div =3D (a=
rgs.v3.ucCntlFlag &
>    2720                                                               ATO=
M_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
>
> There are a lot of other Sparse endian warnings but I haven't looked
> at them.  Here is how to check:  http://lwn.net/Articles/205624/

Hi Dan,

in general I'm not sure that we support any big endian system with that =

code any more.

But Alex wrote most of the atombios code, so that is probably more a =

question for him.

Christian.

> regards,
> dan carpenter
>
>