From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:39591) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UVOVe-0003lp-4a for qemu-devel@nongnu.org; Thu, 25 Apr 2013 11:54:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UVOVX-0000Ex-HX for qemu-devel@nongnu.org; Thu, 25 Apr 2013 11:54:58 -0400 Received: from cantor2.suse.de ([195.135.220.15]:42181 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UVOVX-0000Ed-9N for qemu-devel@nongnu.org; Thu, 25 Apr 2013 11:54:51 -0400 Message-ID: <517951CA.4080309@suse.de> Date: Thu, 25 Apr 2013 17:54:50 +0200 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1366898737-6201-1-git-send-email-imammedo@redhat.com> <1366898737-6201-4-git-send-email-imammedo@redhat.com> In-Reply-To: <1366898737-6201-4-git-send-email-imammedo@redhat.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 03/15] acpi_piix4: add infrastructure to send CPU hot-plug GPE to guest List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Igor Mammedov Cc: peter.maydell@linaro.org, aliguori@us.ibm.com, ehabkost@redhat.com, mst@redhat.com, stefano.stabellini@eu.citrix.com, qemu-devel@nongnu.org, quintela@redhat.com, anthony.perard@citrix.com, pbonzini@redhat.com Am 25.04.2013 16:05, schrieb Igor Mammedov: > * introduce processor status bitmask visible to guest at 0xaf00 addr, > where ACPI asl code expects it > * set bit corresponding to APIC ID in processor status bitmask on > receiving CPU hot-plug notification > * trigger CPU hot-plug SCI, to notify guest about CPU hot-plug event >=20 > Signed-off-by: Igor Mammedov > --- > Note: > gpe_cpu.sts isn't need to be migrated, since CPU hotpluging during > migration just doesn't work, since destination QEMU has to be started > with all present in guest CPUs (including hotplugged). > i.e. src-qemu -smp 2,max-cpus=3D4; cpu-add id=3D2; dst-qemu -smp 3,ma= x-cpus=3D4 > Destination QEMU will recreate the same gpe_cpu.sts=3Dt'111' bitmap a= s > on source by calling qemu_for_each_cpu(piix4_init_cpu_status, &s->gpe= _cpu); > since it has been started with 3 CPUs on command line. >=20 > v7: > * s/struct cpu_status/struct CPUStatus/ > v6: > * drop gpe_cpu.sts migration hunks > v5: > * add optional vmstate subsection if there was CPU hotplug event > * remove unused Error* > * use qemu_for_each_cpu() instead of recursion over QOM tree > v4: > * added spec for QEMU-Seabios interface > * added PIIX4_ prefix to PROC_ defines > v3: > * s/get_firmware_id()/get_arch_id()/ due rebase > * s/cpu_add_notifier/cpu_added_notifier/ > v2: > * use CPUClass.get_firmware_id() to make code target independent > * bump up vmstate_acpi version > --- > docs/specs/acpi_cpu_hotplug.txt | 22 +++++++++ > hw/acpi/piix4.c | 90 +++++++++++++++++++++++++++++++= +++++++- > 2 files changed, 110 insertions(+), 2 deletions(-) > create mode 100644 docs/specs/acpi_cpu_hotplug.txt Thanks, since it no longer depends on migration discussions, applied to qom-cpu (with changes below: struct typedef and symmetric read/write): https://github.com/afaerber/qemu-cpu/commits/qom-cpu Andreas diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index ebd1af9..c4af1cc 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -59,9 +59,9 @@ struct pci_status { uint32_t down; }; -struct CPUStatus { +typedef struct CPUStatus { uint8_t sts[PIIX4_PROC_LEN]; -}; +} CPUStatus; typedef struct PIIX4PMState { PCIDevice dev; @@ -92,7 +92,7 @@ typedef struct PIIX4PMState { uint8_t disable_s4; uint8_t s4_val; - struct CPUStatus gpe_cpu; + CPUStatus gpe_cpu; Notifier cpu_added_notifier; } PIIX4PMState; @@ -597,10 +597,10 @@ static const MemoryRegionOps piix4_pci_ops =3D { }, }; -static uint64_t cpu_status_read(void *opaque, hwaddr addr, unsigned widt= h) +static uint64_t cpu_status_read(void *opaque, hwaddr addr, unsigned int size) { PIIX4PMState *s =3D opaque; - struct CPUStatus *cpus =3D &s->gpe_cpu; + CPUStatus *cpus =3D &s->gpe_cpu; uint64_t val =3D cpus->sts[addr]; return val; @@ -630,7 +630,7 @@ typedef enum { static void piix4_cpu_hotplug_req(PIIX4PMState *s, CPUState *cpu, HotplugEventType action) { - struct CPUStatus *g =3D &s->gpe_cpu; + CPUStatus *g =3D &s->gpe_cpu; ACPIGPE *gpe =3D &s->ar.gpe; CPUClass *k =3D CPU_GET_CLASS(cpu); int64_t cpu_id; @@ -656,7 +656,7 @@ static void piix4_cpu_added_req(Notifier *n, void *opaque) static void piix4_init_cpu_status(CPUState *cpu, void *data) { - struct CPUStatus *g =3D (struct CPUStatus *)data; + CPUStatus *g =3D (CPUStatus *)data; CPUClass *k =3D CPU_GET_CLASS(cpu); int64_t id =3D k->get_arch_id(cpu); --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg