From mboxrd@z Thu Jan  1 00:00:00 1970
From: Suravee Suthikulanit <suravee.suthikulpanit@amd.com>
Subject: Re: [PATCH] AMD IOMMU: fill msi_desc fields required by
	commit fe017c59
Date: Mon, 6 May 2013 17:43:23 -0500
Message-ID: <5188320B.4090608@amd.com>
References: <517E4C9D02000078000D1812@nat28.tlf.novell.com>
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To: Jan Beulich <JBeulich@suse.com>
Cc: "Shin, Jacob" <Jacob.Shin@amd.com>, xen-devel <xen-devel@lists.xen.org>
List-Id: xen-devel@lists.xenproject.org

This looks fine and tested. Thanks for the patch.

Suravee

On 4/29/2013 3:34 AM, Jan Beulich wrote:
> Since the AMD IOMMU code relies on the x86 generic MSI code, it also
> needs to be updated to match "x86/MSI: cleanup to prepare for multi-
> vector MSI".
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>
> --- a/xen/drivers/passthrough/amd/iommu_init.c
> +++ b/xen/drivers/passthrough/amd/iommu_init.c
> @@ -775,9 +775,16 @@ static bool_t __init set_iommu_interrupt
>       control = pci_conf_read16(iommu->seg, PCI_BUS(iommu->bdf),
>                                 PCI_SLOT(iommu->bdf), PCI_FUNC(iommu->bdf),
>                                 iommu->msi.msi_attrib.pos + PCI_MSI_FLAGS);
> -    iommu->msi.msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
> -    desc->handler = control & PCI_MSI_FLAGS_MASKBIT ?
> -                    &iommu_maskable_msi_type : &iommu_msi_type;
> +    iommu->msi.msi.nvec = 1;
> +    if ( is_mask_bit_support(control) )
> +    {
> +        iommu->msi.msi_attrib.maskbit = 1;
> +        iommu->msi.msi.mpos = msi_mask_bits_reg(iommu->msi.msi_attrib.pos,
> +                                                is_64bit_address(control));
> +        desc->handler = &iommu_maskable_msi_type;
> +    }
> +    else
> +        desc->handler = &iommu_msi_type;
>       ret = request_irq(irq, iommu_interrupt_handler, 0, "amd_iommu", iommu);
>       if ( ret )
>       {
>
>
>