diff for duplicates of <518A8596.7070702@wwwdotorg.org> diff --git a/a/content_digest b/N1/content_digest index 32235fd..57f099e 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,24 +1,25 @@ "ref\01368010660-31465-1-git-send-email-jagarwal@nvidia.com\0" "ref\01368010660-31465-4-git-send-email-jagarwal@nvidia.com\0" - "From\0Stephen Warren <swarren@wwwdotorg.org>\0" + "ref\01368010660-31465-4-git-send-email-jagarwal-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org\0" + "From\0Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>\0" "Subject\0Re: [PATCH 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu\0" "Date\0Wed, 08 May 2013 11:04:22 -0600\0" - "To\0Jay Agarwal <jagarwal@nvidia.com>\0" - "Cc\0linux@arm.linux.org.uk" - thierry.reding@avionic-design.de - ldewangan@nvidia.com - bhelgaas@google.com - olof@lixom.net - hdoyu@nvidia.com - pgaikwad@nvidia.com - mturquette@linaro.org - pdeschrijver@nvidia.com - linux-arm-kernel@lists.infradead.org - linux-tegra@vger.kernel.org - linux-kernel@vger.kernel.org - linux-pci@vger.kernel.org - jtukkinen@nvidia.com - " kthota@nvidia.com\0" + "To\0Jay Agarwal <jagarwal-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" + "Cc\0linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org" + thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org + ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org + bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org + olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org + hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org + pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org + mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + jtukkinen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org + " kthota-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org\0" "\00:1\0" "b\0" "On 05/08/2013 04:57 AM, Jay Agarwal wrote:\n" @@ -82,4 +83,4 @@ "is treated as an error, even though it's a valid HW register value.\n" Perhaps this is related? -386b8736a552e89f86b8d8e6e27c9c8d41b777752de7716dacf3b0ce4b1f1031 +2e437324b7c93d4f99c22a2c2774250c3b9f68cc69059ba7e9373e78edf9d369
diff --git a/a/1.txt b/N2/1.txt index 0c7c281..3bafa3b 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -13,7 +13,7 @@ On 05/08/2013 04:57 AM, Jay Agarwal wrote: > + vdd-supply = <&ldo1_reg>; > + avdd-supply = <&ldo2_reg>; > + -> + pci@3,0 { +> + pci at 3,0 { > + status = "okay"; > + }; > + }; @@ -37,15 +37,15 @@ particular link configuration, but just inherits the default from tegra30.dtsi, which describes a 222 link configuration. I would have expected the following in the Cardhu DT: - pci@1,0 { + pci at 1,0 { nvidia,num-lanes = <4>; }; - pci@2,0 { + pci at 2,0 { nvidia,num-lanes = <1>; }; - pci@3,0 { + pci at 3,0 { status = "okay"; nvidia,num-lanes = <1>; }; diff --git a/a/content_digest b/N2/content_digest index 32235fd..f349cb5 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,24 +1,9 @@ "ref\01368010660-31465-1-git-send-email-jagarwal@nvidia.com\0" "ref\01368010660-31465-4-git-send-email-jagarwal@nvidia.com\0" - "From\0Stephen Warren <swarren@wwwdotorg.org>\0" - "Subject\0Re: [PATCH 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu\0" + "From\0swarren@wwwdotorg.org (Stephen Warren)\0" + "Subject\0[PATCH 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu\0" "Date\0Wed, 08 May 2013 11:04:22 -0600\0" - "To\0Jay Agarwal <jagarwal@nvidia.com>\0" - "Cc\0linux@arm.linux.org.uk" - thierry.reding@avionic-design.de - ldewangan@nvidia.com - bhelgaas@google.com - olof@lixom.net - hdoyu@nvidia.com - pgaikwad@nvidia.com - mturquette@linaro.org - pdeschrijver@nvidia.com - linux-arm-kernel@lists.infradead.org - linux-tegra@vger.kernel.org - linux-kernel@vger.kernel.org - linux-pci@vger.kernel.org - jtukkinen@nvidia.com - " kthota@nvidia.com\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 05/08/2013 04:57 AM, Jay Agarwal wrote:\n" @@ -36,7 +21,7 @@ "> +\t\tvdd-supply = <&ldo1_reg>;\n" "> +\t\tavdd-supply = <&ldo2_reg>;\n" "> +\n" - "> +\t\tpci@3,0 {\n" + "> +\t\tpci at 3,0 {\n" "> +\t\t\tstatus = \"okay\";\n" "> +\t\t};\n" "> +\t};\n" @@ -60,15 +45,15 @@ "tegra30.dtsi, which describes a 222 link configuration. I would have\n" "expected the following in the Cardhu DT:\n" "\n" - "\t\tpci@1,0 {\n" + "\t\tpci at 1,0 {\n" "\t\t\tnvidia,num-lanes = <4>;\n" "\t\t};\n" "\n" - "\t\tpci@2,0 {\n" + "\t\tpci at 2,0 {\n" "\t\t\tnvidia,num-lanes = <1>;\n" "\t\t};\n" "\n" - "\t\tpci@3,0 {\n" + "\t\tpci at 3,0 {\n" "\t\t\tstatus = \"okay\";\n" "\t\t\tnvidia,num-lanes = <1>;\n" "\t\t};\n" @@ -82,4 +67,4 @@ "is treated as an error, even though it's a valid HW register value.\n" Perhaps this is related? -386b8736a552e89f86b8d8e6e27c9c8d41b777752de7716dacf3b0ce4b1f1031 +9ff2e30868036ca7e5a299a7c8e5962fbd0138ef6cf9f09348ca038ee087a98e
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