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From: Zenghui Yu <zenghui.yu@linux.dev>
To: Alexander Graf <agraf@csgraf.de>
Cc: "QEMU Developers" <qemu-devel@nongnu.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Eduardo Habkost" <ehabkost@redhat.com>,
	"Sergio Lopez" <slp@redhat.com>,
	"Peter Collingbourne" <pcc@google.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Cameron Esfahani" <dirty@apple.com>,
	"Roman Bolshakov" <r.bolshakov@yadro.com>,
	qemu-arm <qemu-arm@nongnu.org>, "Frank Yang" <lfy@google.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: Re: [PATCH v12 04/10] hvf: Add Apple Silicon support
Date: Sun, 28 Jul 2024 17:49:50 +0800	[thread overview]
Message-ID: <5191e86e-8e1b-4ecd-b4ac-e71a2204f25d@linux.dev> (raw)
In-Reply-To: <20210916155404.86958-5-agraf@csgraf.de>

Hi Alexander,

On 2021/9/16 23:53, Alexander Graf wrote:

> +int hvf_arch_init_vcpu(CPUState *cpu)
> +{
> +    ARMCPU *arm_cpu = ARM_CPU(cpu);
> +    CPUARMState *env = &arm_cpu->env;
> +    uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match);
> +    uint32_t sregs_cnt = 0;
> +    uint64_t pfr;
> +    hv_return_t ret;
> +    int i;
> +
> +    env->aarch64 = 1;
> +    asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz));
> +
> +    /* Allocate enough space for our sysreg sync */
> +    arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes,
> +                                     sregs_match_len);
> +    arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values,
> +                                    sregs_match_len);
> +    arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t,
> +                                             arm_cpu->cpreg_vmstate_indexes,
> +                                             sregs_match_len);
> +    arm_cpu->cpreg_vmstate_values = g_renew(uint64_t,
> +                                            arm_cpu->cpreg_vmstate_values,
> +                                            sregs_match_len);
> +
> +    memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t));
> +
> +    /* Populate cp list for all known sysregs */
> +    for (i = 0; i < sregs_match_len; i++) {
> +        const ARMCPRegInfo *ri;
> +        uint32_t key = hvf_sreg_match[i].key;
> +
> +        ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
> +        if (ri) {
> +            assert(!(ri->type & ARM_CP_NO_RAW));
> +            hvf_sreg_match[i].cp_idx = sregs_cnt;
> +            arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key);
> +        } else {
> +            hvf_sreg_match[i].cp_idx = -1;
> +        }
> +    }
> +    arm_cpu->cpreg_array_len = sregs_cnt;
> +    arm_cpu->cpreg_vmstate_array_len = sregs_cnt;
> +
> +    assert(write_cpustate_to_list(arm_cpu, false));
> +
> +    /* Set CP_NO_RAW system registers on init */
> +    ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MIDR_EL1,
> +                              arm_cpu->midr);
> +    assert_hvf_ok(ret);
> +
> +    ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MPIDR_EL1,
> +                              arm_cpu->mp_affinity);
> +    assert_hvf_ok(ret);
> +
> +    ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr);
> +    assert_hvf_ok(ret);
> +    pfr |= env->gicv3state ? (1 << 24) : 0;

It seems that this happens before
arm_gicv3_common_realize()/gicv3_set_gicv3state() so we always get a
*NULL* env->gicv3state.

Noticed by starting a guest with '-machine gic-version=3' but the guest
visible ID_AA64PFR0_EL1.GIC is 0.

> +    ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr);
> +    assert_hvf_ok(ret);
> +
> +    /* We're limited to underlying hardware caps, override internal versions */
> +    ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64MMFR0_EL1,
> +                              &arm_cpu->isar.id_aa64mmfr0);
> +    assert_hvf_ok(ret);
> +
> +    return 0;
> +}

Thanks,
Zenghui

  parent reply	other threads:[~2024-07-28  9:50 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-16 15:53 [PATCH v12 00/10] hvf: Implement Apple Silicon Support Alexander Graf
2021-09-16 15:53 ` [PATCH v12 01/10] arm: Move PMC register definitions to internals.h Alexander Graf
2021-09-16 15:53 ` [PATCH v12 02/10] hvf: Add execute to dirty log permission bitmap Alexander Graf
2021-09-16 15:53 ` [PATCH v12 03/10] hvf: Introduce hvf_arch_init() callback Alexander Graf
2021-09-16 15:53 ` [PATCH v12 04/10] hvf: Add Apple Silicon support Alexander Graf
2021-09-21 15:30   ` Peter Maydell
2021-09-21 17:05     ` Alexander Graf
2023-11-30 14:17   ` Philippe Mathieu-Daudé
2023-12-01  9:40     ` Alexander Graf
2024-07-28  9:49   ` Zenghui Yu [this message]
2021-09-16 15:53 ` [PATCH v12 05/10] arm/hvf: Add a WFI handler Alexander Graf
2021-09-16 15:54 ` [PATCH v12 06/10] hvf: arm: Implement -cpu host Alexander Graf
2021-09-16 16:08   ` Philippe Mathieu-Daudé
2021-09-20  9:19     ` Peter Maydell
2021-09-16 15:54 ` [PATCH v12 07/10] hvf: arm: Implement PSCI handling Alexander Graf
2021-09-16 15:54 ` [PATCH v12 08/10] arm: Add Hypervisor.framework build target Alexander Graf
2021-09-16 15:54 ` [PATCH v12 09/10] hvf: arm: Add rudimentary PMC support Alexander Graf
2021-09-16 15:54 ` [PATCH v12 10/10] arm: tcg: Adhere to SMCCC 1.3 section 5.2 Alexander Graf
2021-09-27 10:45   ` Peter Maydell
2021-09-20 10:11 ` [PATCH v12 00/10] hvf: Implement Apple Silicon Support Peter Maydell
2021-09-20 13:15   ` Peter Maydell
2021-09-20 16:17     ` Philippe Mathieu-Daudé
2021-09-20 20:21       ` Alexander Graf
2021-09-21  9:29         ` Philippe Mathieu-Daudé
2021-09-21  9:29           ` Philippe Mathieu-Daudé
2021-09-21 13:30           ` Alexander Graf
2021-09-25 17:22             ` Philippe Mathieu-Daudé
2021-09-25 18:09               ` Peter Maydell
2021-09-25 18:09                 ` Peter Maydell

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