diff for duplicates of <5197DBCA.8050708@prisktech.co.nz> diff --git a/a/1.txt b/N1/1.txt index 8a86c00..0173aae 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -61,7 +61,7 @@ On 19/05/13 01:28, Alexey Charkov wrote: >> * Bit 8+9 (0x300) are ignored on WM8505 as reserved >> */ >> - writel(0x31c, fbi->regbase + REG_GOVRH_YUVRGB); ->> + if (fbi->interface = INTERFACE_VGA) +>> + if (fbi->interface == INTERFACE_VGA) >> + writel(0x338, fbi->regbase + REG_GOVRH_YUVRGB); >> + else >> + writel(0x31c, fbi->regbase + REG_GOVRH_YUVRGB); @@ -80,7 +80,7 @@ On my list of things to do :) >> writel(0xf, fbi->regbase + REG_GOVRH_FHI); >> - writel(4, fbi->regbase + REG_GOVRH_DVO_SET); >> + ->> + if (fbi->interface = INTERFACE_VGA) +>> + if (fbi->interface == INTERFACE_VGA) >> + writel(0xe, fbi->regbase + REG_GOVRH_DVO_SET); >> + else >> + writel(4, fbi->regbase + REG_GOVRH_DVO_SET); @@ -97,7 +97,7 @@ This register defines the h/v syncpolarity and enable/disable for DVO. >> writel(h_end, fbi->regbase + REG_GOVRH_ACTPX_END); >> writel(h_all, fbi->regbase + REG_GOVRH_H_ALLPXL); >> writel(h_sync, fbi->regbase + REG_GOVRH_HDMI_HSYNW); ->> + if (fbi->interface = INTERFACE_VGA) +>> + if (fbi->interface == INTERFACE_VGA) >> + writel(h_sync, fbi->regbase + REG_GOVRH_VGA_HSYNW); > Will it misbehave on LCD if you write to the VGA register unconditionally? Don't know - wouldn't imagine so. I will test it and see. @@ -106,7 +106,7 @@ Don't know - wouldn't imagine so. I will test it and see. >> writel(v_end, fbi->regbase + REG_GOVRH_ACTLN_END); >> writel(v_all, fbi->regbase + REG_GOVRH_V_ALLLN); >> writel(v_sync, fbi->regbase + REG_GOVRH_HDMI_VBISW); ->> + if (fbi->interface = INTERFACE_VGA) +>> + if (fbi->interface == INTERFACE_VGA) >> + writel(info->var.pixclock, fbi->regbase + REG_GOVRH_VGA_VSYNW); > Same here. I would assume that setting the pixclock should not hurt > LCD, which would then simplify the code a little. diff --git a/a/content_digest b/N1/content_digest index 4f1152a..d3ad21e 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,9 @@ "ref\01368868514-18975-1-git-send-email-linux@prisktech.co.nz\0" "ref\01368868514-18975-5-git-send-email-linux@prisktech.co.nz\0" "ref\0CABjd4Yxrk3hXnB5f6u+1HcJjymDZbtQ1F1HXkZ2dzF3dwCrWhg@mail.gmail.com\0" - "From\0Tony Prisk <linux@prisktech.co.nz>\0" - "Subject\0Re: [PATCH 4/4] fb: vt8500: Add VGA output support to wm8505fb driver.\0" - "Date\0Sat, 18 May 2013 19:51:38 +0000\0" + "From\0linux@prisktech.co.nz (Tony Prisk)\0" + "Subject\0[PATCH 4/4] fb: vt8500: Add VGA output support to wm8505fb driver.\0" + "Date\0Sun, 19 May 2013 07:51:38 +1200\0" "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" @@ -70,7 +70,7 @@ ">> * Bit 8+9 (0x300) are ignored on WM8505 as reserved\n" ">> */\n" ">> - writel(0x31c, fbi->regbase + REG_GOVRH_YUVRGB);\n" - ">> + if (fbi->interface = INTERFACE_VGA)\n" + ">> + if (fbi->interface == INTERFACE_VGA)\n" ">> + writel(0x338, fbi->regbase + REG_GOVRH_YUVRGB);\n" ">> + else\n" ">> + writel(0x31c, fbi->regbase + REG_GOVRH_YUVRGB);\n" @@ -89,7 +89,7 @@ ">> writel(0xf, fbi->regbase + REG_GOVRH_FHI);\n" ">> - writel(4, fbi->regbase + REG_GOVRH_DVO_SET);\n" ">> +\n" - ">> + if (fbi->interface = INTERFACE_VGA)\n" + ">> + if (fbi->interface == INTERFACE_VGA)\n" ">> + writel(0xe, fbi->regbase + REG_GOVRH_DVO_SET);\n" ">> + else\n" ">> + writel(4, fbi->regbase + REG_GOVRH_DVO_SET);\n" @@ -106,7 +106,7 @@ ">> writel(h_end, fbi->regbase + REG_GOVRH_ACTPX_END);\n" ">> writel(h_all, fbi->regbase + REG_GOVRH_H_ALLPXL);\n" ">> writel(h_sync, fbi->regbase + REG_GOVRH_HDMI_HSYNW);\n" - ">> + if (fbi->interface = INTERFACE_VGA)\n" + ">> + if (fbi->interface == INTERFACE_VGA)\n" ">> + writel(h_sync, fbi->regbase + REG_GOVRH_VGA_HSYNW);\n" "> Will it misbehave on LCD if you write to the VGA register unconditionally?\n" "Don't know - wouldn't imagine so. I will test it and see.\n" @@ -115,7 +115,7 @@ ">> writel(v_end, fbi->regbase + REG_GOVRH_ACTLN_END);\n" ">> writel(v_all, fbi->regbase + REG_GOVRH_V_ALLLN);\n" ">> writel(v_sync, fbi->regbase + REG_GOVRH_HDMI_VBISW);\n" - ">> + if (fbi->interface = INTERFACE_VGA)\n" + ">> + if (fbi->interface == INTERFACE_VGA)\n" ">> + writel(info->var.pixclock, fbi->regbase + REG_GOVRH_VGA_VSYNW);\n" "> Same here. I would assume that setting the pixclock should not hurt\n" "> LCD, which would then simplify the code a little.\n" @@ -125,4 +125,4 @@ "Regards\n" Tony Prisk -785da54075714e34c3bad833d3189a5e84a1e9f6bd0daaf0de75277c88f439d8 +1f5843778b2177025ff8e90d5d007612b8d2fe06626ec24fc7d04cc1748d8970
diff --git a/a/1.txt b/N2/1.txt index 8a86c00..0173aae 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -61,7 +61,7 @@ On 19/05/13 01:28, Alexey Charkov wrote: >> * Bit 8+9 (0x300) are ignored on WM8505 as reserved >> */ >> - writel(0x31c, fbi->regbase + REG_GOVRH_YUVRGB); ->> + if (fbi->interface = INTERFACE_VGA) +>> + if (fbi->interface == INTERFACE_VGA) >> + writel(0x338, fbi->regbase + REG_GOVRH_YUVRGB); >> + else >> + writel(0x31c, fbi->regbase + REG_GOVRH_YUVRGB); @@ -80,7 +80,7 @@ On my list of things to do :) >> writel(0xf, fbi->regbase + REG_GOVRH_FHI); >> - writel(4, fbi->regbase + REG_GOVRH_DVO_SET); >> + ->> + if (fbi->interface = INTERFACE_VGA) +>> + if (fbi->interface == INTERFACE_VGA) >> + writel(0xe, fbi->regbase + REG_GOVRH_DVO_SET); >> + else >> + writel(4, fbi->regbase + REG_GOVRH_DVO_SET); @@ -97,7 +97,7 @@ This register defines the h/v syncpolarity and enable/disable for DVO. >> writel(h_end, fbi->regbase + REG_GOVRH_ACTPX_END); >> writel(h_all, fbi->regbase + REG_GOVRH_H_ALLPXL); >> writel(h_sync, fbi->regbase + REG_GOVRH_HDMI_HSYNW); ->> + if (fbi->interface = INTERFACE_VGA) +>> + if (fbi->interface == INTERFACE_VGA) >> + writel(h_sync, fbi->regbase + REG_GOVRH_VGA_HSYNW); > Will it misbehave on LCD if you write to the VGA register unconditionally? Don't know - wouldn't imagine so. I will test it and see. @@ -106,7 +106,7 @@ Don't know - wouldn't imagine so. I will test it and see. >> writel(v_end, fbi->regbase + REG_GOVRH_ACTLN_END); >> writel(v_all, fbi->regbase + REG_GOVRH_V_ALLLN); >> writel(v_sync, fbi->regbase + REG_GOVRH_HDMI_VBISW); ->> + if (fbi->interface = INTERFACE_VGA) +>> + if (fbi->interface == INTERFACE_VGA) >> + writel(info->var.pixclock, fbi->regbase + REG_GOVRH_VGA_VSYNW); > Same here. I would assume that setting the pixclock should not hurt > LCD, which would then simplify the code a little. diff --git a/a/content_digest b/N2/content_digest index 4f1152a..d035391 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -3,8 +3,14 @@ "ref\0CABjd4Yxrk3hXnB5f6u+1HcJjymDZbtQ1F1HXkZ2dzF3dwCrWhg@mail.gmail.com\0" "From\0Tony Prisk <linux@prisktech.co.nz>\0" "Subject\0Re: [PATCH 4/4] fb: vt8500: Add VGA output support to wm8505fb driver.\0" - "Date\0Sat, 18 May 2013 19:51:38 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "Date\0Sun, 19 May 2013 07:51:38 +1200\0" + "To\0Alexey Charkov <alchark@gmail.com>\0" + "Cc\0VT8500/WM8505 Linux Kernel <vt8500-wm8505-linux-kernel@googlegroups.com>" + Florian Tobias Schandinat <FlorianSchandinat@gmx.de> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + tomi.valkeinen@ti.com + " linux-fbdev@vger.kernel.org <linux-fbdev@vger.kernel.org>\0" "\00:1\0" "b\0" "On 19/05/13 01:28, Alexey Charkov wrote:\n" @@ -70,7 +76,7 @@ ">> * Bit 8+9 (0x300) are ignored on WM8505 as reserved\n" ">> */\n" ">> - writel(0x31c, fbi->regbase + REG_GOVRH_YUVRGB);\n" - ">> + if (fbi->interface = INTERFACE_VGA)\n" + ">> + if (fbi->interface == INTERFACE_VGA)\n" ">> + writel(0x338, fbi->regbase + REG_GOVRH_YUVRGB);\n" ">> + else\n" ">> + writel(0x31c, fbi->regbase + REG_GOVRH_YUVRGB);\n" @@ -89,7 +95,7 @@ ">> writel(0xf, fbi->regbase + REG_GOVRH_FHI);\n" ">> - writel(4, fbi->regbase + REG_GOVRH_DVO_SET);\n" ">> +\n" - ">> + if (fbi->interface = INTERFACE_VGA)\n" + ">> + if (fbi->interface == INTERFACE_VGA)\n" ">> + writel(0xe, fbi->regbase + REG_GOVRH_DVO_SET);\n" ">> + else\n" ">> + writel(4, fbi->regbase + REG_GOVRH_DVO_SET);\n" @@ -106,7 +112,7 @@ ">> writel(h_end, fbi->regbase + REG_GOVRH_ACTPX_END);\n" ">> writel(h_all, fbi->regbase + REG_GOVRH_H_ALLPXL);\n" ">> writel(h_sync, fbi->regbase + REG_GOVRH_HDMI_HSYNW);\n" - ">> + if (fbi->interface = INTERFACE_VGA)\n" + ">> + if (fbi->interface == INTERFACE_VGA)\n" ">> + writel(h_sync, fbi->regbase + REG_GOVRH_VGA_HSYNW);\n" "> Will it misbehave on LCD if you write to the VGA register unconditionally?\n" "Don't know - wouldn't imagine so. I will test it and see.\n" @@ -115,7 +121,7 @@ ">> writel(v_end, fbi->regbase + REG_GOVRH_ACTLN_END);\n" ">> writel(v_all, fbi->regbase + REG_GOVRH_V_ALLLN);\n" ">> writel(v_sync, fbi->regbase + REG_GOVRH_HDMI_VBISW);\n" - ">> + if (fbi->interface = INTERFACE_VGA)\n" + ">> + if (fbi->interface == INTERFACE_VGA)\n" ">> + writel(info->var.pixclock, fbi->regbase + REG_GOVRH_VGA_VSYNW);\n" "> Same here. I would assume that setting the pixclock should not hurt\n" "> LCD, which would then simplify the code a little.\n" @@ -125,4 +131,4 @@ "Regards\n" Tony Prisk -785da54075714e34c3bad833d3189a5e84a1e9f6bd0daaf0de75277c88f439d8 +815824f6f1969a30a08a758719b3820ec614fbea4541e673ec3ccb4e0acea756
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