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Message-ID: <519A7249.1030302@gmail.com>
Date:   Mon, 20 May 2013 11:58:17 -0700
From:   David Daney <ddaney.cavm@gmail.com>
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To:     "Maciej W. Rozycki" <macro@linux-mips.org>
CC:     Sanjay Lal <sanjayl@kymasys.com>, kvm@vger.kernel.org,
        linux-mips@linux-mips.org, Ralf Baechle <ralf@linux-mips.org>,
        Gleb Natapov <gleb@redhat.com>,
        Marcelo Tosatti <mtosatti@redhat.com>
Subject: Re: [PATCH 00/18] KVM/MIPS32: Support for the new Virtualization
 ASE (VZ-ASE)
References: <n> <1368942460-15577-1-git-send-email-sanjayl@kymasys.com> <519A4640.6060202@gmail.com> <456B70C6-A896-4B94-B8EF-DE6ED26CE859@kymasys.com> <alpine.LFD.2.03.1305201930570.10753@linux-mips.org>
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On 05/20/2013 11:36 AM, Maciej W. Rozycki wrote:
> On Mon, 20 May 2013, Sanjay Lal wrote:
>
>> (1) Newer versions of the MIPS architecture define scratch registers for
>> just this purpose, but since we have to support standard MIPS32R2
>> processors, we use the DDataLo Register (CP0 Register 28, Select 3) as a
>> scratch register to save k0 and save k1 @ a known offset from EBASE.
>
>   That's rather risky as the implementation of this register (and its
> presence in the first place) is processor-specific.  Do you maintain a
> list of PRId values the use of this register is safe with?
>

FWIW:  The MIPS-VZ architecture module requires the presence of CP0 
scratch registers that can be used for this in the exception handlers 
without having to worry about using these implementation dependent 
registers.  For the trap-and-emulate only version, there really is no 
choice other than to re-purpose some of the existing CP0 registers.

David Daney