From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:34479) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UfQnG-0000b8-9p for qemu-devel@nongnu.org; Thu, 23 May 2013 04:22:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UfQn7-0001EU-Qn for qemu-devel@nongnu.org; Thu, 23 May 2013 04:22:38 -0400 Received: from lhrrgout.huawei.com ([194.213.3.17]:50876) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UfQn7-0001E6-IU for qemu-devel@nongnu.org; Thu, 23 May 2013 04:22:29 -0400 Message-ID: <519DD1BD.2020208@huawei.com> Date: Thu, 23 May 2013 10:22:21 +0200 From: Claudio Fontana MIME-Version: 1.0 References: <5141F36E.10004@huawei.com> <519DCEC8.8060000@huawei.com> In-Reply-To: <519DCEC8.8060000@huawei.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH 4/4] tcg/aarch64: more ops in preparation of tlb lookup List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Paolo Bonzini , qemu-devel@nongnu.org, Richard Henderson add SUBS to the arithmetic instructions and add a shift parameter to all arithmetic instructions, so we can make use of shifted registers. Signed-off-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index da859c7..5440659 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -190,6 +190,7 @@ enum aarch64_ldst_op_type { /* type of operation */ enum aarch64_arith_opc { ARITH_ADD = 0x0b, ARITH_SUB = 0x4b, + ARITH_SUBS = 0x6b, ARITH_AND = 0x0a, ARITH_OR = 0x2a, ARITH_XOR = 0x4a @@ -410,12 +411,20 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, } static inline void tcg_out_arith(TCGContext *s, enum aarch64_arith_opc opc, - int ext, int rd, int rn, int rm) + int ext, int rd, int rn, int rm, int shift_imm) { /* Using shifted register arithmetic operations */ /* if extended registry operation (64bit) just or with 0x80 << 24 */ - unsigned int base = ext ? (0x80 | opc) << 24 : opc << 24; - tcg_out32(s, base | rm << 16 | rn << 5 | rd); + unsigned int shift, base = ext ? (0x80 | opc) << 24 : opc << 24; + if (shift_imm == 0) { + shift = 0; + } else if (shift_imm > 0) { + shift = shift_imm << 10 | 1 << 22; + } else /* (shift_imm < 0) */ { + shift = (-shift_imm) << 10; + } + + tcg_out32(s, base | rm << 16 | shift | rn << 5 | rd); } static inline void tcg_out_mul(TCGContext *s, int ext, int rd, int rn, int rm) @@ -597,6 +606,15 @@ static inline void tcg_out_tst(TCGContext *s, int ext, int rn, tcg_out32(s, base | (pattern_n - 1) << 10 | rn << 5); } +/* and a register with a bit pattern, similarly to TST, no flags change */ +static inline void tcg_out_andi(TCGContext *s, int ext, int rd, + int rn, tcg_target_ulong pattern_n) +{ + /* using AND 0x12000000. Ext requires 4. */ + unsigned int base = ext ? 0x92400000 : 0x12000000; + tcg_out32(s, base | (pattern_n - 1) << 10 | rn << 5); +} + static inline void tcg_out_ret(TCGContext *s) { /* emit RET { LR } */ @@ -870,27 +888,27 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_add_i64: ext = 1; case INDEX_op_add_i32: - tcg_out_arith(s, ARITH_ADD, ext, args[0], args[1], args[2]); + tcg_out_arith(s, ARITH_ADD, ext, args[0], args[1], args[2], 0); break; case INDEX_op_sub_i64: ext = 1; case INDEX_op_sub_i32: - tcg_out_arith(s, ARITH_SUB, ext, args[0], args[1], args[2]); + tcg_out_arith(s, ARITH_SUB, ext, args[0], args[1], args[2], 0); break; case INDEX_op_and_i64: ext = 1; case INDEX_op_and_i32: - tcg_out_arith(s, ARITH_AND, ext, args[0], args[1], args[2]); + tcg_out_arith(s, ARITH_AND, ext, args[0], args[1], args[2], 0); break; case INDEX_op_or_i64: ext = 1; case INDEX_op_or_i32: - tcg_out_arith(s, ARITH_OR, ext, args[0], args[1], args[2]); + tcg_out_arith(s, ARITH_OR, ext, args[0], args[1], args[2], 0); break; case INDEX_op_xor_i64: ext = 1; case INDEX_op_xor_i32: - tcg_out_arith(s, ARITH_XOR, ext, args[0], args[1], args[2]); + tcg_out_arith(s, ARITH_XOR, ext, args[0], args[1], args[2], 0); break; case INDEX_op_mul_i64: ext = 1; @@ -939,7 +957,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, if (const_args[2]) { /* ROR / EXTR Wd, Wm, Wm, 32 - m */ tcg_out_rotl(s, ext, args[0], args[1], args[2]); } else { - tcg_out_arith(s, ARITH_SUB, ext, args[2], TCG_REG_XZR, args[2]); + tcg_out_arith(s, ARITH_SUB, ext, args[2], TCG_REG_XZR, args[2], 0); tcg_out_shiftrot_reg(s, SRR_ROR, ext, args[0], args[1], args[2]); } break; -- 1.8.1