From: Jagan Teki <jagannadh.teki@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [U-Boot,1/2,V5] spi: Add support for preamble bytes
Date: Mon, 03 Jun 2013 00:08:39 +0530 [thread overview]
Message-ID: <51AB912F.1020407@gmail.com> (raw)
In-Reply-To: <1369807838-18683-2-git-send-email-rajeshwari.s@samsung.com>
On 29-05-2013 01:40, Rajeshwari Shinde wrote:
> A SPI slave may take time to react to a request. For SPI flash devices
> this time is defined as one bit time, or a whole byte for 'fast read'
> mode.
>
> If the SPI slave is another CPU, then the time it takes to react may
> vary. It is convenient to allow the slave device to tag the start of
> the actual reply so that the host can determine when this 'preamble'
> finishes and the actual message starts.
>
> Add a preamble flag to the available SPI flags. If supported by the
> driver then it will ignore any received bytes before the preamble
> on each transaction. This ensures that reliable communication with
> the slave is possible.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
>
> ---
> Changes in V2:
> - None
> Changes in V3:
> - None.
> Changes in V4:
> - None.
> Changes in V5:
> - In commit message header changed SPI to spi.
> include/spi.h | 5 +++++
> 1 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/include/spi.h b/include/spi.h
> index 3fe2e1e..1638b50 100644
> --- a/include/spi.h
> +++ b/include/spi.h
> @@ -37,11 +37,16 @@
> #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
> #define SPI_3WIRE 0x10 /* SI/SO signals shared */
> #define SPI_LOOP 0x20 /* loopback mode */
> +#define SPI_SLAVE 0x40 /* slave mode */
> +#define SPI_PREAMBLE 0x80 /* Skip preamble bytes */
>
> /* SPI transfer flags */
> #define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */
> #define SPI_XFER_END 0x02 /* Deassert CS after transfer */
>
> +/* Header byte that marks the start of the message */
> +#define SPI_PREAMBLE_END_BYTE 0xec
> +
> /*-----------------------------------------------------------------------
> * Representation of a SPI slave, i.e. what we're communicating with.
> *
Applied to u-boot-spi/master
--
Thanks,
Jagan.
next prev parent reply other threads:[~2013-06-02 18:38 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-29 6:10 [U-Boot] [PATCH 0/2 V5] spi: Enable SPI_PREAMBLE Mode Rajeshwari Shinde
2013-05-29 6:10 ` [U-Boot] [PATCH 1/2 V5] spi: Add support for preamble bytes Rajeshwari Shinde
2013-06-02 17:24 ` Jagan Teki
2013-06-02 17:55 ` Simon Glass
2013-06-02 18:00 ` Jagan Teki
2013-06-02 18:03 ` Simon Glass
2013-06-02 18:19 ` [U-Boot] [U-Boot,1/2,V5] " Jagan Teki
2013-06-02 18:38 ` Jagan Teki [this message]
2013-05-29 6:10 ` [U-Boot] [PATCH 2/2 V5] spi: exynos: Support SPI_PREAMBLE mode Rajeshwari Shinde
2013-06-02 17:41 ` Jagan Teki
2013-06-02 18:00 ` Simon Glass
2013-06-02 18:20 ` [U-Boot] [U-Boot, 2/2, " Jagan Teki
2013-06-02 18:38 ` Jagan Teki
2013-05-30 4:38 ` [U-Boot] [PATCH 0/2 V5] spi: Enable SPI_PREAMBLE Mode Simon Glass
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=51AB912F.1020407@gmail.com \
--to=jagannadh.teki@gmail.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.