From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38892) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UjRJ7-0002xL-Hv for qemu-devel@nongnu.org; Mon, 03 Jun 2013 05:44:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UjRIy-0007BP-JN for qemu-devel@nongnu.org; Mon, 03 Jun 2013 05:44:05 -0400 Received: from lhrrgout.huawei.com ([194.213.3.17]:10848) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UjRIy-0007Aw-B0 for qemu-devel@nongnu.org; Mon, 03 Jun 2013 05:43:56 -0400 Message-ID: <51AC653B.8080701@huawei.com> Date: Mon, 3 Jun 2013 11:43:23 +0200 From: Claudio Fontana MIME-Version: 1.0 References: <51A8E339.5000500@huawei.com> <51A8E46F.5030707@huawei.com> <51A8F4D4.7000805@twiddle.net> In-Reply-To: <51A8F4D4.7000805@twiddle.net> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/4] tcg/aarch64: more low level ops in preparation of tlb, lookup List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: Laurent Desnogues , Peter Maydell , Jani Kokkonen , qemu-devel@nongnu.org On 31.05.2013 21:07, Richard Henderson wrote: > On 05/31/2013 10:57 AM, Jani Kokkonen wrote: >> + ARITH_SUBS = 0x6b, > > Any reason you're adding SUBS here, but not ANDS? I also forgot ANDS, I'll add them and reorder. >> +/* encode a logical immediate, mapping user parameter >> + M=set bits pattern length to S=M-1 */ >> +static inline unsigned int >> +aarch64_limm(unsigned int m, unsigned int r) >> +{ >> + assert(m > 0); >> + return r << 16 | (m - 1) << 10; >> +} >> + >> +/* test a register against an immediate bit pattern made of >> + M set bits rotated right by R. >> + Examples: >> + to test a 32/64 reg against 0x00000007, pass M = 3, R = 0. >> + to test a 32/64 reg against 0x000000ff, pass M = 8, R = 0. >> + to test a 32bit reg against 0xff000000, pass M = 8, R = 8. >> + to test a 32bit reg against 0xff0000ff, pass M = 16, R = 8. >> + */ >> +static inline void tcg_out_tst(TCGContext *s, int ext, TCGReg rn, >> + unsigned int m, unsigned int r) >> +{ >> + /* using TST alias of ANDS XZR, Xn,#bimm64 0x7200001f */ >> + unsigned int base = ext ? 0xf240001f : 0x7200001f; >> + tcg_out32(s, base | aarch64_limm(m, r) | rn << 5); >> +} >> + >> +/* and a register with a bit pattern, similarly to TST, no flags change */ >> +static inline void tcg_out_andi(TCGContext *s, int ext, TCGReg rd, TCGReg rn, >> + unsigned int m, unsigned int r) >> +{ >> + /* using AND 0x12000000 */ >> + unsigned int base = ext ? 0x92400000 : 0x12000000; >> + tcg_out32(s, base | aarch64_limm(m, r) | rn << 5 | rd); >> +} >> + > > This should be a separate patch, since it's not related to the tcg_out_arith > change. > Agreed. Claudio