From mboxrd@z Thu Jan 1 00:00:00 1970 From: mikedunn@newsguy.com (Mike Dunn) Date: Thu, 06 Jun 2013 17:48:41 -0700 Subject: pxa27x and pinctrl-single In-Reply-To: References: <51AF7404.3090003@newsguy.com> <51B0C7E8.5090308@newsguy.com> Message-ID: <51B12DE9.9040908@newsguy.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 06/06/2013 04:58 PM, Haojian Zhuang wrote: > On 7 June 2013 01:33, Mike Dunn wrote: >> [...] >> >> Yes, but currently pinctrl-single only supports writing one register for a given >> pin (with multiple pins sharing a register if bit-per-mux==true). On pxa27x, a >> pin's alt function is determined by the values written to both the GAFRx and the >> GPDRx registers, so I think that pinctrl-single may need to allow a device tree >> to specify multiple reg/value/mask sets for any one pin. I don't have a >> pxa3xx/mmp developer's manual handy, but from the code it appears that on these >> arches the direction register is irrelevant to the mux setting. >> > > No, it's not need to access both GAFRx & GPDRx. Let's focus on PXA27x first. > > GPIO ?x? Alternate Function Select Bits (where x = 112 through 120) > A bit-pair in this register determines the corresponding GPIO pin?s > functionality as one of the alternate functions that is mapped to it or as a > generic GPIO pin. > > 0b00 = The corresponding GPIO pin (GPIO) is used as a general- > purpose I/O. > 0b01 = The corresponding GPIO pin (GPIO) is used for its alternate > function 1. > 0b10 = The corresponding GPIO pin (GPIO) is used for its alternate > function 2. > 0b11 = The corresponding GPIO pin (GPIO) is used for its alternate > function 3. > > We can see that GAFRx configures the pinmux. That's all. We can use > pinctrl-single > driver to cover this. But on the pxa27x there are usually *two* meanings for any one of the 3 alt functions, depending on the direction. As a random example... gpio28 alt fn 0b01 is AC97_BITCLK if the direction is input, but is I2S_BITCLK if the direction is output (from PXA27x Developer's Manual, Table 24-2). > > I know that you're also talking the implementation in gpio-pxa driver. > __gpio_is_occupied() checks both GAFRx & GPDRx. Because this GPIO > pin should be configured as GPIO input. Actually we could also discard the > checking. > > So there's no relationship between GAFRx and GPDRx. But I am thinking on pxa27x there is... see my example above. Perhaps this is not true for the later Marvell arches and you are missing this point? Or else I am stating the obvious to you and I am missing your point. In either case, thanks for your patience. Thanks, Mike From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mike Dunn Subject: Re: pxa27x and pinctrl-single Date: Thu, 06 Jun 2013 17:48:41 -0700 Message-ID: <51B12DE9.9040908@newsguy.com> References: <51AF7404.3090003@newsguy.com> <51B0C7E8.5090308@newsguy.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Haojian Zhuang Cc: "Manjunathappa, Prakash" , "devicetree-discuss@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" , Linus Walleij List-Id: devicetree@vger.kernel.org On 06/06/2013 04:58 PM, Haojian Zhuang wrote: > On 7 June 2013 01:33, Mike Dunn wrote: >> [...] >> >> Yes, but currently pinctrl-single only supports writing one register for= a given >> pin (with multiple pins sharing a register if bit-per-mux=3D=3Dtrue). O= n pxa27x, a >> pin's alt function is determined by the values written to both the GAFRx= and the >> GPDRx registers, so I think that pinctrl-single may need to allow a devi= ce tree >> to specify multiple reg/value/mask sets for any one pin. I don't have a >> pxa3xx/mmp developer's manual handy, but from the code it appears that o= n these >> arches the direction register is irrelevant to the mux setting. >> > = > No, it's not need to access both GAFRx & GPDRx. Let's focus on PXA27x fir= st. > = > GPIO =91x=92 Alternate Function Select Bits (where x =3D 112 through 120) > A bit-pair in this register determines the corresponding GPIO pin=92s > functionality as one of the alternate functions that is mapped to it or a= s a > generic GPIO pin. > = > 0b00 =3D The corresponding GPIO pin (GPIO) is used as a general- > purpose I/O. > 0b01 =3D The corresponding GPIO pin (GPIO) is used for its alternate > function 1. > 0b10 =3D The corresponding GPIO pin (GPIO) is used for its alternate > function 2. > 0b11 =3D The corresponding GPIO pin (GPIO) is used for its alternate > function 3. > = > We can see that GAFRx configures the pinmux. That's all. We can use > pinctrl-single > driver to cover this. But on the pxa27x there are usually *two* meanings for any one of the 3 alt functions, depending on the direction. As a random example... gpio28 alt fn 0b01 is AC97_BITCLK if the direction is input, but is I2S_BITCLK if the direction is output (from PXA27x Developer's Manual, Table 24-2). > = > I know that you're also talking the implementation in gpio-pxa driver. > __gpio_is_occupied() checks both GAFRx & GPDRx. Because this GPIO > pin should be configured as GPIO input. Actually we could also discard the > checking. > = > So there's no relationship between GAFRx and GPDRx. But I am thinking on pxa27x there is... see my example above. Perhaps this= is not true for the later Marvell arches and you are missing this point? Or e= lse I am stating the obvious to you and I am missing your point. In either case, thanks for your patience. Thanks, Mike