diff for duplicates of <51B21012.2030302@wwwdotorg.org> diff --git a/a/1.txt b/N1/1.txt index 9fb5f66..33342e9 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -3,9 +3,9 @@ On 06/07/2013 06:19 AM, Paul Walmsley wrote: > 51MHz (as required by the DFLL GFD) and to use the PLL_P clock source. > > This patch is a collaboration with Peter De Schrijver -> <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>. +> <pdeschrijver@nvidia.com>. > -> Thanks to Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> for identifying the +> Thanks to Laxman Dewangan <ldewangan@nvidia.com> for identifying the > requirement to keep the DFLL clocks enabled to resolve PWR_I2C timeout > issues. diff --git a/a/content_digest b/N1/content_digest index edc3594..8e23b6e 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,19 +1,9 @@ "ref\020130607121505.21868.72360.stgit@dusk.lan\0" "ref\020130607121858.21868.73882.stgit@dusk.lan\0" - "ref\020130607121858.21868.73882.stgit-orwA252wQtA@public.gmane.org\0" - "From\0Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>\0" - "Subject\0Re: [PATCH 2/3] clk: tegra: T114: add DFLL source clocks\0" + "From\0swarren@wwwdotorg.org (Stephen Warren)\0" + "Subject\0[PATCH 2/3] clk: tegra: T114: add DFLL source clocks\0" "Date\0Fri, 07 Jun 2013 10:53:38 -0600\0" - "To\0Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>" - " Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" - "Cc\0linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" - mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - Andrew Chew <achew-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - Matthew Longnecker <mlongnecker-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 06/07/2013 06:19 AM, Paul Walmsley wrote:\n" @@ -21,9 +11,9 @@ "> 51MHz (as required by the DFLL GFD) and to use the PLL_P clock source.\n" "> \n" "> This patch is a collaboration with Peter De Schrijver\n" - "> <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>.\n" + "> <pdeschrijver@nvidia.com>.\n" "> \n" - "> Thanks to Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> for identifying the\n" + "> Thanks to Laxman Dewangan <ldewangan@nvidia.com> for identifying the\n" "> requirement to keep the DFLL clocks enabled to resolve PWR_I2C timeout\n" "> issues.\n" "\n" @@ -45,4 +35,4 @@ "\n" For reference, include/dt-bindings/clock/tegra*-car.h. -c548957c376ebc6dee88c216a8f568801b47deb910ef2b92a4aed4b3c055c5bf +de4906614706c273ad6807828b80a826ef569f8c06bd9a7face447477be3d8b2
diff --git a/a/1.txt b/N2/1.txt index 9fb5f66..33342e9 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -3,9 +3,9 @@ On 06/07/2013 06:19 AM, Paul Walmsley wrote: > 51MHz (as required by the DFLL GFD) and to use the PLL_P clock source. > > This patch is a collaboration with Peter De Schrijver -> <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>. +> <pdeschrijver@nvidia.com>. > -> Thanks to Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> for identifying the +> Thanks to Laxman Dewangan <ldewangan@nvidia.com> for identifying the > requirement to keep the DFLL clocks enabled to resolve PWR_I2C timeout > issues. diff --git a/a/content_digest b/N2/content_digest index edc3594..407fe48 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,19 +1,18 @@ "ref\020130607121505.21868.72360.stgit@dusk.lan\0" "ref\020130607121858.21868.73882.stgit@dusk.lan\0" - "ref\020130607121858.21868.73882.stgit-orwA252wQtA@public.gmane.org\0" - "From\0Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>\0" + "From\0Stephen Warren <swarren@wwwdotorg.org>\0" "Subject\0Re: [PATCH 2/3] clk: tegra: T114: add DFLL source clocks\0" "Date\0Fri, 07 Jun 2013 10:53:38 -0600\0" - "To\0Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>" - " Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" - "Cc\0linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" - mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - Andrew Chew <achew-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - Matthew Longnecker <mlongnecker-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" + "To\0Paul Walmsley <pwalmsley@nvidia.com>" + " Hiroshi Doyu <hdoyu@nvidia.com>\0" + "Cc\0linux-tegra@vger.kernel.org" + mturquette@linaro.org + Andrew Chew <achew@nvidia.com> + Peter De Schrijver <pdeschrijver@nvidia.com> + linux-kernel@vger.kernel.org + Matthew Longnecker <mlongnecker@nvidia.com> + Laxman Dewangan <ldewangan@nvidia.com> + " linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 06/07/2013 06:19 AM, Paul Walmsley wrote:\n" @@ -21,9 +20,9 @@ "> 51MHz (as required by the DFLL GFD) and to use the PLL_P clock source.\n" "> \n" "> This patch is a collaboration with Peter De Schrijver\n" - "> <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>.\n" + "> <pdeschrijver@nvidia.com>.\n" "> \n" - "> Thanks to Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> for identifying the\n" + "> Thanks to Laxman Dewangan <ldewangan@nvidia.com> for identifying the\n" "> requirement to keep the DFLL clocks enabled to resolve PWR_I2C timeout\n" "> issues.\n" "\n" @@ -45,4 +44,4 @@ "\n" For reference, include/dt-bindings/clock/tegra*-car.h. -c548957c376ebc6dee88c216a8f568801b47deb910ef2b92a4aed4b3c055c5bf +cac6d24b4f9ea22b9f76da52f3f58c5b04a788e748bed13eb0e00e0c089475c7
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