diff for duplicates of <51B6D239.5030905@nvidia.com> diff --git a/a/1.txt b/N1/1.txt index 19ef1e2..97b62e9 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -12,7 +12,7 @@ On Friday 07 June 2013 10:36 PM, Paul Walmsley wrote: >>> line, the DVCO will not oscillate, although reads and writes to the >>> DFLL IP block will complete. >>> ->>> Thanks to Aleksandr Frid <afrid-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> for identifying this and +>>> Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and >>> saving hours of debugging time. >>> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h >>> void tegra114_clock_tune_cpu_trimmers_high(void); @@ -34,7 +34,7 @@ address register to driver? >> provider, hence removing the existing custom >> tegra_periph_reset_{de,}assert() APIs. > OK, will take a look to see if this can be done without getting in the way -> of Prashant's work. I'd naïvely assume that it might be best to convert +> of Prashant's work. I'd na?vely assume that it might be best to convert > these as part of his series - that way we won't duplicate effort. > > Prashant, what stage are you at in the conversion? If you're close to diff --git a/a/content_digest b/N1/content_digest index f482672..c0de324 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,18 +2,10 @@ "ref\020130607121901.21868.65416.stgit@dusk.lan\0" "ref\051B21105.1080301@wwwdotorg.org\0" "ref\0alpine.DEB.2.02.1306071703050.7753@utopia.booyaka.com\0" - "ref\0alpine.DEB.2.02.1306071703050.7753-rwI8Ez+7Ko+d5PgPZx9QOdBPR1lH4CV8@public.gmane.org\0" - "From\0Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" - "Subject\0Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control\0" + "From\0pgaikwad@nvidia.com (Prashant Gaikwad)\0" + "Subject\0[PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control\0" "Date\0Tue, 11 Jun 2013 13:01:05 +0530\0" - "To\0Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" - "Cc\0Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>" - linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> - Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - Aleksandr Frid <afrid-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Friday 07 June 2013 10:36 PM, Paul Walmsley wrote:\n" @@ -30,7 +22,7 @@ ">>> line, the DVCO will not oscillate, although reads and writes to the\n" ">>> DFLL IP block will complete.\n" ">>>\n" - ">>> Thanks to Aleksandr Frid <afrid-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> for identifying this and\n" + ">>> Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and\n" ">>> saving hours of debugging time.\n" ">>> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h\n" ">>> void tegra114_clock_tune_cpu_trimmers_high(void);\n" @@ -52,7 +44,7 @@ ">> provider, hence removing the existing custom\n" ">> tegra_periph_reset_{de,}assert() APIs.\n" "> OK, will take a look to see if this can be done without getting in the way\n" - "> of Prashant's work. I'd na\303\257vely assume that it might be best to convert\n" + "> of Prashant's work. I'd na?vely assume that it might be best to convert\n" "> these as part of his series - that way we won't duplicate effort.\n" ">\n" "> Prashant, what stage are you at in the conversion? If you're close to\n" @@ -64,4 +56,4 @@ "\n" > - Paul -f8266da861e5bf800139fcd3697f44c4e660e9043588a3caa8bbec4391b63c68 +d4166a748a46cccd914f1c5b534a08254b1e07c8619e7190ee22d18fdcda165c
diff --git a/a/1.txt b/N2/1.txt index 19ef1e2..709b165 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -12,7 +12,7 @@ On Friday 07 June 2013 10:36 PM, Paul Walmsley wrote: >>> line, the DVCO will not oscillate, although reads and writes to the >>> DFLL IP block will complete. >>> ->>> Thanks to Aleksandr Frid <afrid-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> for identifying this and +>>> Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and >>> saving hours of debugging time. >>> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h >>> void tegra114_clock_tune_cpu_trimmers_high(void); diff --git a/a/content_digest b/N2/content_digest index f482672..369301d 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -2,18 +2,17 @@ "ref\020130607121901.21868.65416.stgit@dusk.lan\0" "ref\051B21105.1080301@wwwdotorg.org\0" "ref\0alpine.DEB.2.02.1306071703050.7753@utopia.booyaka.com\0" - "ref\0alpine.DEB.2.02.1306071703050.7753-rwI8Ez+7Ko+d5PgPZx9QOdBPR1lH4CV8@public.gmane.org\0" - "From\0Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" + "From\0Prashant Gaikwad <pgaikwad@nvidia.com>\0" "Subject\0Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control\0" "Date\0Tue, 11 Jun 2013 13:01:05 +0530\0" - "To\0Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" - "Cc\0Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>" - linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> - Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - Aleksandr Frid <afrid-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0" + "To\0Paul Walmsley <pwalmsley@nvidia.com>\0" + "Cc\0Stephen Warren <swarren@wwwdotorg.org>" + linux-tegra@vger.kernel.org <linux-tegra@vger.kernel.org> + mturquette@linaro.org <mturquette@linaro.org> + Peter De Schrijver <pdeschrijver@nvidia.com> + Aleksandr Frid <afrid@nvidia.com> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" "\00:1\0" "b\0" "On Friday 07 June 2013 10:36 PM, Paul Walmsley wrote:\n" @@ -30,7 +29,7 @@ ">>> line, the DVCO will not oscillate, although reads and writes to the\n" ">>> DFLL IP block will complete.\n" ">>>\n" - ">>> Thanks to Aleksandr Frid <afrid-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> for identifying this and\n" + ">>> Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and\n" ">>> saving hours of debugging time.\n" ">>> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h\n" ">>> void tegra114_clock_tune_cpu_trimmers_high(void);\n" @@ -64,4 +63,4 @@ "\n" > - Paul -f8266da861e5bf800139fcd3697f44c4e660e9043588a3caa8bbec4391b63c68 +272aff2049d3d4a06855efe1826acc2445a9b2858a626b05e40f437d3287ca96
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