Re: [PATCH v2] drm/i915: Do not flush caches on RT, print a warning instead

[Sebastian Andrzej Siewior <bigeasy@linutronix.de>]

On 06/09/2013 01:45 PM, Carsten Emde wrote:
> Invalidating and flushing all caches may introduce long latencies of up
> to several milliseconds. Do not execute it in PREEMPT_RT_FULL kernels,
> warn once instead and propose to pin all GPU renderering tasks to a
> single CPU, if possible.
> 
> Original commit:
> 25ff1195f8a0b3724541ae7bbe331b4296de9c06 upstream.
> 
> Original log:
> In order to fully serialize access to the fenced region and the update
> to the fence register we need to take extreme measures on SNB+, and
> manually flush writes to memory prior to writing the fence register in
> conjunction with the memory barriers placed around the register write.
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Carsten Emde <C.Emde@osadl.org>

Oh boy.

Chris, I have a few questions:
- is the wbinvd() required even on the local CPU or just the remote?
  According to bugzilla non-smp works fine. If so, you open code
  wbinvd_on_all_cpus()
- is it possible to replace the wbinvd() with clflush() ?
- is the problem going away if every process doing graphics is pinned
  to single CPU and the wbindv() call is avoided?

Sebastian