diff for duplicates of <51BEBDAF.7000201@ti.com> diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index 5959ca5..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/x-diff; name="0001-omap5-add-qspi-support.patch" -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename="0001-omap5-add-qspi-support.patch" diff --git a/a/2.txt b/a/2.txt deleted file mode 100644 index b8d3714..0000000 --- a/a/2.txt +++ /dev/null @@ -1,99 +0,0 @@ ->From 42584552cfe3055abebe4ac8a824fc5d527db9e2 Mon Sep 17 00:00:00 2001 -From: Matt Porter <mporter@ti.com> -Date: Mon, 6 May 2013 15:31:45 -0400 -Subject: [PATCH 1/5] omap5: add qspi support - -Add QSPI definitions and clock configuration support. - -Signed-off-by: Matt Porter <mporter@ti.com> -Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> ---- - arch/arm/cpu/armv7/omap5/hw_data.c | 5 ++++- - arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 + - arch/arm/include/asm/arch-omap5/omap.h | 3 +++ - arch/arm/include/asm/arch-omap5/spl.h | 1 + - arch/arm/include/asm/omap_common.h | 1 + - 5 files changed, 10 insertions(+), 1 deletions(-) - -diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c -index 716b931..c7a27e2 100644 ---- a/arch/arm/cpu/armv7/omap5/hw_data.c -+++ b/arch/arm/cpu/armv7/omap5/hw_data.c -@@ -194,7 +194,7 @@ static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { - {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ -- {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */ -+ {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1} /* 20 MHz */ - }; - - static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { -@@ -488,6 +488,7 @@ void enable_basic_clocks(void) - (*prcm)->cm_wkup_wdtimer2_clkctrl, - (*prcm)->cm_l4per_uart3_clkctrl, - (*prcm)->cm_l4per_i2c1_clkctrl, -+ (*prcm)->cm_l4per_qspi_clkctrl, - 0 - }; - -@@ -516,6 +517,8 @@ void enable_basic_clocks(void) - clk_modules_explicit_en_essential, - 1); - -+ setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); -+ - /* Enable SCRM OPT clocks for PER and CORE dpll */ - setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, - OPTFCLKEN_SCRM_PER_MASK); -diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c -index 426b50f..a7aa922 100644 ---- a/arch/arm/cpu/armv7/omap5/prcm-regs.c -+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c -@@ -933,6 +933,7 @@ struct prcm_regs const dra7xx_prcm = { - .cm_l4per_gpio8_clkctrl = 0x4a009818, - .cm_l4per_mmcsd3_clkctrl = 0x4a009820, - .cm_l4per_mmcsd4_clkctrl = 0x4a009828, -+ .cm_l4per_qspi_clkctrl = 0x4a009838, - .cm_l4per_uart1_clkctrl = 0x4a009840, - .cm_l4per_uart2_clkctrl = 0x4a009848, - .cm_l4per_uart3_clkctrl = 0x4a009850, -diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h -index 9ecc096..ab526ae 100644 ---- a/arch/arm/include/asm/arch-omap5/omap.h -+++ b/arch/arm/include/asm/arch-omap5/omap.h -@@ -67,6 +67,9 @@ - /* GPMC */ - #define OMAP54XX_GPMC_BASE 0x50000000 - -+/* QSPI */ -+#define QSPI_BASE 0x4B300000 -+ - /* - * Hardware Register Details - */ -diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h -index d4d353c..8905cb8 100644 ---- a/arch/arm/include/asm/arch-omap5/spl.h -+++ b/arch/arm/include/asm/arch-omap5/spl.h -@@ -31,6 +31,7 @@ - #define BOOT_DEVICE_MMC1 5 - #define BOOT_DEVICE_MMC2 6 - #define BOOT_DEVICE_MMC2_2 7 -+#define BOOT_DEVICE_SPI 10 - - #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 - #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 -diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h -index a678bc0..55deacb 100644 ---- a/arch/arm/include/asm/omap_common.h -+++ b/arch/arm/include/asm/omap_common.h -@@ -280,6 +280,7 @@ struct prcm_regs { - u32 cm_l4per_mmcsd4_clkctrl; - u32 cm_l4per_msprohg_clkctrl; - u32 cm_l4per_slimbus2_clkctrl; -+ u32 cm_l4per_qspi_clkctrl; - u32 cm_l4per_uart1_clkctrl; - u32 cm_l4per_uart2_clkctrl; - u32 cm_l4per_uart3_clkctrl; --- -1.7.1 diff --git a/a/3.hdr b/a/3.hdr deleted file mode 100644 index b76f860..0000000 --- a/a/3.hdr +++ /dev/null @@ -1,4 +0,0 @@ -Content-Type: text/x-diff; name="0002-spi-add-TI-QSPI-driver.patch" -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename="0002-spi-add-TI-QSPI-driver.patch" diff --git a/a/3.txt b/a/3.txt deleted file mode 100644 index aa266ab..0000000 --- a/a/3.txt +++ /dev/null @@ -1,297 +0,0 @@ ->From 47b503ff2d3f331010a19874a4d3e8f4bb88c604 Mon Sep 17 00:00:00 2001 -From: Matt Porter <mporter@ti.com> -Date: Mon, 6 May 2013 15:32:15 -0400 -Subject: [PATCH 2/5] spi: add TI QSPI driver - -Adds a SPI master driver for the TI QSPI peripheral. - -Signed-off-by: Matt Porter <mporter@ti.com> -Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> ---- - drivers/spi/Makefile | 1 + - drivers/spi/ti_qspi.c | 262 +++++++++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 263 insertions(+), 0 deletions(-) - create mode 100644 drivers/spi/ti_qspi.c - -diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile -index d08609e..f51033d 100644 ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -54,6 +54,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o - COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o - COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o - COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o -+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o - COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o - - COBJS := $(COBJS-y) -diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c -new file mode 100644 -index 0000000..1973b85 ---- /dev/null -+++ b/drivers/spi/ti_qspi.c -@@ -0,0 +1,262 @@ -+/* -+ * TI QSPI driver -+ * -+ * Copyright (C) 2013, Texas Instruments, Incorporated -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include <common.h> -+#include <asm/io.h> -+#include <asm/arch/omap.h> -+#include <malloc.h> -+#include <spi.h> -+ -+struct qspi_slave { -+ struct spi_slave slave; -+ unsigned int mode; -+ u32 cmd; -+ u32 dc; -+}; -+ -+#define to_qspi_slave(s) container_of(s, struct qspi_slave, slave) -+ -+struct qspi_regs { -+ u32 pid; -+ u32 pad0[3]; -+ u32 sysconfig; -+ u32 pad1[3]; -+ u32 intr_status_raw_set; -+ u32 intr_status_enabled_clear; -+ u32 intr_enable_set; -+ u32 intr_enable_clear; -+ u32 intc_eoi; -+ u32 pad2[3]; -+ u32 spi_clock_cntrl; -+ u32 spi_dc; -+ u32 spi_cmd; -+ u32 spi_status; -+ u32 spi_data; -+ u32 spi_setup0; -+ u32 spi_setup1; -+ u32 spi_setup2; -+ u32 spi_setup3; -+ u32 spi_switch; -+ u32 spi_data1; -+ u32 spi_data2; -+ u32 spi_data3; -+}; -+ -+static struct qspi_regs *qspi = (struct qspi_regs *)QSPI_BASE; -+ -+#define QSPI_TIMEOUT 2000000 -+ -+#define QSPI_FCLK 192000000 -+ -+/* Clock Control */ -+#define QSPI_CLK_EN (1 << 31) -+#define QSPI_CLK_DIV_MAX 0xffff -+ -+/* Command */ -+#define QSPI_EN_CS(n) (n << 28) -+#define QSPI_WLEN(n) ((n-1) << 19) -+#define QSPI_3_PIN (1 << 18) -+#define QSPI_RD_SNGL (1 << 16) -+#define QSPI_WR_SNGL (2 << 16) -+#define QSPI_INVAL (4 << 16) -+ -+/* Device Control */ -+#define QSPI_DD(m, n) (m << (3 + n*8)) -+#define QSPI_CKPHA(n) (1 << (2 + n*8)) -+#define QSPI_CSPOL(n) (1 << (1 + n*8)) -+#define QSPI_CKPOL(n) (1 << (n*8)) -+ -+/* Status */ -+#define QSPI_WC (1 << 1) -+#define QSPI_BUSY (1 << 0) -+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY) -+#define QSPI_XFER_DONE QSPI_WC -+ -+int spi_cs_is_valid(unsigned int bus, unsigned int cs) -+{ -+ return 1; -+} -+ -+void spi_cs_activate(struct spi_slave *slave) -+{ -+ /* CS handled in xfer */ -+ return; -+} -+ -+void spi_cs_deactivate(struct spi_slave *slave) -+{ -+ /* CS handled in xfer */ -+ return; -+} -+ -+void spi_init(void) -+{ -+ /* nothing to do */ -+} -+ -+void spi_set_speed(struct spi_slave *slave, uint hz) -+{ -+ uint clk_div; -+ -+ if (!hz) -+ clk_div = 0; -+ else -+ clk_div = (QSPI_FCLK / hz) - 1; -+ -+ debug("%s: hz: %d, clock divider %d\n", __func__, hz, clk_div); -+ -+ /* disable SCLK */ -+ writel(readl(&qspi->spi_clock_cntrl) & ~QSPI_CLK_EN, &qspi->spi_clock_cntrl); -+ -+ if (clk_div < 0) { -+ debug("%s: clock divider < 0, using /1 divider\n", __func__); -+ clk_div = 0; -+ } -+ -+ if (clk_div > QSPI_CLK_DIV_MAX) { -+ debug("%s: clock divider >%d , using /%d divider\n", -+ __func__, QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1); -+ clk_div = QSPI_CLK_DIV_MAX; -+ } -+ -+ /* enable SCLK */ -+ writel(QSPI_CLK_EN | clk_div, &qspi->spi_clock_cntrl); -+ debug("%s: spi_clock_cntrl %08x\n", __func__, readl(&qspi->spi_clock_cntrl)); -+} -+ -+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, -+ unsigned int max_hz, unsigned int mode) -+{ -+ struct qspi_slave *qslave; -+ -+ qslave = spi_alloc_slave(struct qspi_slave, bus, cs); -+ if (!qslave) -+ return NULL; -+ -+ spi_set_speed(&qslave->slave, max_hz); -+ qslave->mode = mode; -+ debug("%s: bus:%i cs:%i mode:%i\n", __func__, bus, cs, mode); -+ -+ return &qslave->slave; -+} -+ -+void spi_free_slave(struct spi_slave *slave) -+{ -+ struct qspi_slave *qslave = to_qspi_slave(slave); -+ free(qslave); -+} -+ -+int spi_claim_bus(struct spi_slave *slave) -+{ -+ debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); -+ -+ writel(0, &qspi->spi_dc); -+ writel(0, &qspi->spi_cmd); -+ writel(0, &qspi->spi_data); -+ -+ return 0; -+} -+ -+void spi_release_bus(struct spi_slave *slave) -+{ -+ debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); -+ -+ writel(0, &qspi->spi_dc); -+ writel(0, &qspi->spi_cmd); -+ writel(0, &qspi->spi_data); -+} -+ -+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, -+ void *din, unsigned long flags) -+{ -+ struct qspi_slave *qslave = to_qspi_slave(slave); -+ uint words = bitlen >> 3; /* fixed 8-bit word length */ -+ const uchar *txp = dout; -+ uchar *rxp = din; -+ uint status; -+ int timeout; -+ -+ debug("%s: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n", __func__, -+ slave->bus, slave->cs, bitlen, words, flags); -+ if (bitlen == 0) -+ return -1; -+ -+ if (bitlen % 8) { -+ flags |= SPI_XFER_END; -+ return -1; -+ } -+ -+ /* setup command reg */ -+ qslave->cmd = 0; -+ qslave->cmd |= QSPI_WLEN(8); -+ qslave->cmd |= QSPI_EN_CS(slave->cs); -+ if (flags & SPI_3WIRE) -+ qslave->cmd |= QSPI_3_PIN; -+ qslave->cmd |= 0xfff; -+ -+ /* setup device control reg */ -+ qslave->dc = 0; -+ if (qslave->mode & SPI_CPHA) -+ qslave->dc |= QSPI_CKPHA(slave->cs); -+ if (qslave->mode & SPI_CPOL) -+ qslave->dc |= QSPI_CKPOL(slave->cs); -+ if (qslave->mode & SPI_CS_HIGH) -+ qslave->dc |= QSPI_CSPOL(slave->cs); -+ -+ while (words--) { -+ if (txp) { -+ debug("tx cmd %08x dc %08x data %02x\n", -+ qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp); -+ writel(*txp++, &qspi->spi_data); -+ writel(qslave->dc, &qspi->spi_dc); -+ writel(qslave->cmd | QSPI_WR_SNGL, &qspi->spi_cmd); -+ status = readl(&qspi->spi_status); -+ timeout = QSPI_TIMEOUT; -+ while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { -+ if (--timeout < 0) { -+ printf("QSPI tx timed out\n"); -+ return -1; -+ } -+ status = readl(&qspi->spi_status); -+ } -+ debug("tx done, status %08x\n", status); -+ } -+ if (rxp) { -+ debug("rx cmd %08x dc %08x\n", -+ qslave->cmd | QSPI_RD_SNGL, qslave->dc); -+ writel(qslave->dc, &qspi->spi_dc); -+ writel(qslave->cmd | QSPI_RD_SNGL, &qspi->spi_cmd); -+ status = readl(&qspi->spi_status); -+ timeout = QSPI_TIMEOUT; -+ while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { -+ if (--timeout < 0) { -+ printf("QSPI rx timed out\n"); -+ return -1; -+ } -+ status = readl(&qspi->spi_status); -+ } -+ *rxp++ = readl(&qspi->spi_data); -+ debug("rx done, status %08x, read %02x\n", -+ status, *(rxp-1)); -+ } -+ } -+ -+ /* Terminate frame */ -+ if (flags & SPI_XFER_END) -+ writel(qslave->cmd | QSPI_INVAL, &qspi->spi_cmd); -+ -+ return 0; -+} --- -1.7.1 diff --git a/a/4.hdr b/a/4.hdr deleted file mode 100644 index b3055d2..0000000 --- a/a/4.hdr +++ /dev/null @@ -1,6 +0,0 @@ -Content-Type: text/x-diff; - name="0003-dra7xx_evm-add-SPL-API-QSPI-and-serial-flash-support.patch" -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename*0="0003-dra7xx_evm-add-SPL-API-QSPI-and-serial-flash-support.pa"; - filename*1="tch" diff --git a/a/4.txt b/a/4.txt deleted file mode 100644 index ff6db1f..0000000 --- a/a/4.txt +++ /dev/null @@ -1,64 +0,0 @@ ->From 89b1ad9848df89817dc8bac7ea12a71d811921ce Mon Sep 17 00:00:00 2001 -From: Matt Porter <mporter@ti.com> -Date: Mon, 6 May 2013 15:33:19 -0400 -Subject: [PATCH 3/5] dra7xx_evm: add SPL API, QSPI, and serial flash support - -Enables support for SPI SPL, QSPI and Spansion serial flash device -on the EVM. Configures pin muxes for QSPI mode. - -Signed-off-by: Matt Porter <mporter@ti.com> -Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> ---- - board/ti/dra7xx/mux_data.h | 10 ++++++++++ - include/configs/dra7xx_evm.h | 17 +++++++++++++++++ - 2 files changed, 27 insertions(+), 0 deletions(-) - -diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h -index 5a91966..b26a9be 100644 ---- a/board/ti/dra7xx/mux_data.h -+++ b/board/ti/dra7xx/mux_data.h -@@ -53,6 +53,16 @@ const struct pad_conf_entry core_padconf_array_essential[] = { - {UART1_RTSN, (IEN | PTU | PDIS | M3)}, - {I2C1_SDA, (IEN | PTU | PDIS | M0)}, - {I2C1_SCL, (IEN | PTU | PDIS | M0)}, -+ {GPMC_A13, (PTU | IEN | M1)}, /* QSPI1_RTCLK */ -+ {GPMC_A18, (PTU | IEN | M1)}, /* QSPI1_SCLK */ -+ {GPMC_A17, (PTU | IEN | M1)}, /* QSPI1_D[0] */ -+ {GPMC_A16, (PTU | IEN | M1)}, /* QSPI1_D[1] */ -+ {GPMC_A15, (PTU | IEN | M1)}, /* QSPI1_D[2] */ -+ {GPMC_A14, (PTU | IEN | M1)}, /* QSPI1_D[3] */ -+ {GPMC_CS2, (PTU | M1)}, /* QSPI1_CS[0] */ -+ {GPMC_CS3, (PTU | M1)}, /* QSPI1_CS[1] */ -+ {GPMC_A3, (PTU | M1)}, /* QSPI1_CS[2] */ -+ {GPMC_A4, (PTU | M1)}, /* QSPI1_CS[3] */ - }; - - const struct pad_conf_entry core_padconf_array_non_essential[] = { -diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h -index 2518352..3671e45 100644 ---- a/include/configs/dra7xx_evm.h -+++ b/include/configs/dra7xx_evm.h -@@ -56,4 +56,21 @@ - - #define EMIF1_EMIF2 - -+/* SPI */ -+#define CONFIG_TI_QSPI -+#define CONFIG_SPI_FLASH -+#define CONFIG_SPI_FLASH_SPANSION -+#define CONFIG_CMD_SF -+#define CONFIG_CMD_SPI -+#define CONFIG_SF_DEFAULT_SPEED 12000000 -+#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 -+ -+/* SPI SPL */ -+#define CONFIG_SPL_SPI_SUPPORT -+#define CONFIG_SPL_SPI_LOAD -+#define CONFIG_SPL_SPI_FLASH_SUPPORT -+#define CONFIG_SPL_SPI_BUS 0 -+#define CONFIG_SPL_SPI_CS 0 -+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 -+ - #endif /* __CONFIG_DRA7XX_EVM_H */ --- -1.7.1 diff --git a/a/5.hdr b/a/5.hdr deleted file mode 100644 index 9f43b04..0000000 --- a/a/5.hdr +++ /dev/null @@ -1,6 +0,0 @@ -Content-Type: text/x-diff; - name="0004-drivers-mtd-spi-Modify-read-write-command-for-sfl256.patch" -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename*0="0004-drivers-mtd-spi-Modify-read-write-command-for-sfl256.pa"; - filename*1="tch" diff --git a/a/5.txt b/a/5.txt deleted file mode 100644 index deeaee2..0000000 --- a/a/5.txt +++ /dev/null @@ -1,81 +0,0 @@ ->From e4139e66b956d17a9157a7b6d055e9f8c585041d Mon Sep 17 00:00:00 2001 -From: Sourav Poddar <sourav.poddar@ti.com> -Date: Fri, 7 Jun 2013 17:15:36 +0530 -Subject: [PATCH 4/5] drivers: mtd: spi: Modify read/write command for sfl256s flash. - -Reading using the already supported read command is causing regression -even while reading 4k bytes, as a result doing a page by page read. - -At the end of the write sequence, write enable latch should be disabled and -re enabled while doing the next page programming. - -Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> ---- - drivers/mtd/spi/spi_flash.c | 39 ++++++++++++++++++++++++++++++++++----- - 1 files changed, 34 insertions(+), 5 deletions(-) - -diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c -index 111185a..8c3a2cf 100644 ---- a/drivers/mtd/spi/spi_flash.c -+++ b/drivers/mtd/spi/spi_flash.c -@@ -117,6 +117,12 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, - if (ret) - break; - -+ ret = spi_flash_cmd_write_disable(flash); -+ if (ret < 0) { -+ printf("SF: disabling write failed\n"); -+ break; -+ } -+ - byte_addr += chunk_len; - if (byte_addr == page_size) { - page_addr++; -@@ -147,17 +153,40 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, - int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, - size_t len, void *data) - { -- u8 cmd[5]; -+ unsigned long page_addr, byte_addr, page_size; -+ size_t chunk_len, actual; -+ int ret = 0; -+ u8 cmd[4]; - - /* Handle memory-mapped SPI */ - if (flash->memory_map) - memcpy(data, flash->memory_map + offset, len); -+ page_size = flash->page_size; -+ page_addr = offset / page_size; -+ byte_addr = offset % page_size; -+ -+ cmd[0] = CMD_READ_ARRAY_SLOW; -+ for (actual = 0; actual < len; actual += chunk_len) { -+ chunk_len = min(len - actual, page_size - byte_addr); -+ -+ cmd[1] = page_addr >> 8; -+ cmd[2] = page_addr; -+ cmd[3] = byte_addr; -+ -+ ret = spi_flash_read_common(flash, cmd, sizeof(cmd), data + actual, chunk_len); -+ if (ret < 0) { -+ debug("SF: read failed"); -+ break; -+ } - -- cmd[0] = CMD_READ_ARRAY_FAST; -- spi_flash_addr(offset, cmd); -- cmd[4] = 0x00; -+ byte_addr += chunk_len; -+ if (byte_addr == page_size) { -+ page_addr++; -+ byte_addr = 0; -+ } -+ } - -- return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len); -+ return ret; - } - - int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, --- -1.7.1 diff --git a/a/content_digest b/N1/content_digest index 462ad79..aa95c2f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -12,16 +12,10 @@ "ref\051BEB89A.3090105@ti.com\0" "ref\0CAD6G_RRNT5ukFovS1Spa7uMmX72kLpZ-YycfcdDdESTMHnNU9Q@mail.gmail.com\0" "From\0Sourav Poddar <sourav.poddar@ti.com>\0" - "Subject\0Re: [U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device\0" + "Subject\0[U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device\0" "Date\0Mon, 17 Jun 2013 13:11:35 +0530\0" - "To\0Jagan Teki <jagannadh.teki@gmail.com>\0" - "Cc\0Rajendra nayak <rnayak@ti.com>" - jagannadha.sutradharudu-teki@xilinx.com - Felipe Balbi <balbi@ti.com> - u-boot@lists.denx.de - linux-mtd@lists.infradead.org - " Tom Rini <trini@ti.com>\0" - "\01:1\0" + "To\0u-boot@lists.denx.de\0" + "\00:1\0" "b\0" "Hi Jagan,\n" "On Monday 17 June 2013 01:04 PM, Jagan Teki wrote:\n" @@ -366,558 +360,5 @@ "> --\n" "> Thanks,\n" > Jagan. - "\01:2\0" - "fn\00001-omap5-add-qspi-support.patch\0" - "b\0" - ">From 42584552cfe3055abebe4ac8a824fc5d527db9e2 Mon Sep 17 00:00:00 2001\n" - "From: Matt Porter <mporter@ti.com>\n" - "Date: Mon, 6 May 2013 15:31:45 -0400\n" - "Subject: [PATCH 1/5] omap5: add qspi support\n" - "\n" - "Add QSPI definitions and clock configuration support.\n" - "\n" - "Signed-off-by: Matt Porter <mporter@ti.com>\n" - "Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>\n" - "---\n" - " arch/arm/cpu/armv7/omap5/hw_data.c | 5 ++++-\n" - " arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 +\n" - " arch/arm/include/asm/arch-omap5/omap.h | 3 +++\n" - " arch/arm/include/asm/arch-omap5/spl.h | 1 +\n" - " arch/arm/include/asm/omap_common.h | 1 +\n" - " 5 files changed, 10 insertions(+), 1 deletions(-)\n" - "\n" - "diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c\n" - "index 716b931..c7a27e2 100644\n" - "--- a/arch/arm/cpu/armv7/omap5/hw_data.c\n" - "+++ b/arch/arm/cpu/armv7/omap5/hw_data.c\n" - "@@ -194,7 +194,7 @@ static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {\n" - " \t{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},\t\t/* 26 MHz */\n" - " \t{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},\t/* 27 MHz */\n" - " \t{10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},\t\t/* 38.4 MHz */\n" - "-\t{96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}\t\t/* 20 MHz */\n" - "+\t{96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}\t\t/* 20 MHz */\n" - " };\n" - " \n" - " static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {\n" - "@@ -488,6 +488,7 @@ void enable_basic_clocks(void)\n" - " \t\t(*prcm)->cm_wkup_wdtimer2_clkctrl,\n" - " \t\t(*prcm)->cm_l4per_uart3_clkctrl,\n" - " \t\t(*prcm)->cm_l4per_i2c1_clkctrl,\n" - "+\t\t(*prcm)->cm_l4per_qspi_clkctrl,\n" - " \t\t0\n" - " \t};\n" - " \n" - "@@ -516,6 +517,8 @@ void enable_basic_clocks(void)\n" - " \t\t\t clk_modules_explicit_en_essential,\n" - " \t\t\t 1);\n" - " \n" - "+\tsetbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));\n" - "+\n" - " \t/* Enable SCRM OPT clocks for PER and CORE dpll */\n" - " \tsetbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,\n" - " \t\t\tOPTFCLKEN_SCRM_PER_MASK);\n" - "diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c\n" - "index 426b50f..a7aa922 100644\n" - "--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c\n" - "+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c\n" - "@@ -933,6 +933,7 @@ struct prcm_regs const dra7xx_prcm = {\n" - " \t.cm_l4per_gpio8_clkctrl\t\t\t= 0x4a009818,\n" - " \t.cm_l4per_mmcsd3_clkctrl\t\t= 0x4a009820,\n" - " \t.cm_l4per_mmcsd4_clkctrl\t\t= 0x4a009828,\n" - "+\t.cm_l4per_qspi_clkctrl\t\t\t= 0x4a009838,\n" - " \t.cm_l4per_uart1_clkctrl\t\t\t= 0x4a009840,\n" - " \t.cm_l4per_uart2_clkctrl\t\t\t= 0x4a009848,\n" - " \t.cm_l4per_uart3_clkctrl\t\t\t= 0x4a009850,\n" - "diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h\n" - "index 9ecc096..ab526ae 100644\n" - "--- a/arch/arm/include/asm/arch-omap5/omap.h\n" - "+++ b/arch/arm/include/asm/arch-omap5/omap.h\n" - "@@ -67,6 +67,9 @@\n" - " /* GPMC */\n" - " #define OMAP54XX_GPMC_BASE\t0x50000000\n" - " \n" - "+/* QSPI */\n" - "+#define QSPI_BASE\t\t0x4B300000\n" - "+\n" - " /*\n" - " * Hardware Register Details\n" - " */\n" - "diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h\n" - "index d4d353c..8905cb8 100644\n" - "--- a/arch/arm/include/asm/arch-omap5/spl.h\n" - "+++ b/arch/arm/include/asm/arch-omap5/spl.h\n" - "@@ -31,6 +31,7 @@\n" - " #define BOOT_DEVICE_MMC1 5\n" - " #define BOOT_DEVICE_MMC2 6\n" - " #define BOOT_DEVICE_MMC2_2\t7\n" - "+#define BOOT_DEVICE_SPI\t\t10\n" - " \n" - " #define MMC_BOOT_DEVICES_START\tBOOT_DEVICE_MMC1\n" - " #define MMC_BOOT_DEVICES_END\tBOOT_DEVICE_MMC2_2\n" - "diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h\n" - "index a678bc0..55deacb 100644\n" - "--- a/arch/arm/include/asm/omap_common.h\n" - "+++ b/arch/arm/include/asm/omap_common.h\n" - "@@ -280,6 +280,7 @@ struct prcm_regs {\n" - " \tu32 cm_l4per_mmcsd4_clkctrl;\n" - " \tu32 cm_l4per_msprohg_clkctrl;\n" - " \tu32 cm_l4per_slimbus2_clkctrl;\n" - "+\tu32 cm_l4per_qspi_clkctrl;\n" - " \tu32 cm_l4per_uart1_clkctrl;\n" - " \tu32 cm_l4per_uart2_clkctrl;\n" - " \tu32 cm_l4per_uart3_clkctrl;\n" - "-- \n" - 1.7.1 - "\01:3\0" - "fn\00002-spi-add-TI-QSPI-driver.patch\0" - "b\0" - ">From 47b503ff2d3f331010a19874a4d3e8f4bb88c604 Mon Sep 17 00:00:00 2001\n" - "From: Matt Porter <mporter@ti.com>\n" - "Date: Mon, 6 May 2013 15:32:15 -0400\n" - "Subject: [PATCH 2/5] spi: add TI QSPI driver\n" - "\n" - "Adds a SPI master driver for the TI QSPI peripheral.\n" - "\n" - "Signed-off-by: Matt Porter <mporter@ti.com>\n" - "Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>\n" - "---\n" - " drivers/spi/Makefile | 1 +\n" - " drivers/spi/ti_qspi.c | 262 +++++++++++++++++++++++++++++++++++++++++++++++++\n" - " 2 files changed, 263 insertions(+), 0 deletions(-)\n" - " create mode 100644 drivers/spi/ti_qspi.c\n" - "\n" - "diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile\n" - "index d08609e..f51033d 100644\n" - "--- a/drivers/spi/Makefile\n" - "+++ b/drivers/spi/Makefile\n" - "@@ -54,6 +54,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o\n" - " COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o\n" - " COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o\n" - " COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o\n" - "+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o\n" - " COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o\n" - " \n" - " COBJS\t:= $(COBJS-y)\n" - "diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c\n" - "new file mode 100644\n" - "index 0000000..1973b85\n" - "--- /dev/null\n" - "+++ b/drivers/spi/ti_qspi.c\n" - "@@ -0,0 +1,262 @@\n" - "+/*\n" - "+ * TI QSPI driver\n" - "+ *\n" - "+ * Copyright (C) 2013, Texas Instruments, Incorporated\n" - "+ *\n" - "+ * This program is free software; you can redistribute it and/or\n" - "+ * modify it under the terms of the GNU General Public License as\n" - "+ * published by the Free Software Foundation; either version 2 of\n" - "+ * the License, or (at your option) any later version.\n" - "+ *\n" - "+ * This program is distributed in the hope that it will be useful,\n" - "+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n" - "+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the\n" - "+ * GNU General Public License for more details.\n" - "+ */\n" - "+\n" - "+#include <common.h>\n" - "+#include <asm/io.h>\n" - "+#include <asm/arch/omap.h>\n" - "+#include <malloc.h>\n" - "+#include <spi.h>\n" - "+\n" - "+struct qspi_slave {\n" - "+\tstruct spi_slave slave;\n" - "+\tunsigned int mode;\n" - "+\tu32 cmd;\n" - "+\tu32 dc;\n" - "+};\n" - "+\n" - "+#define to_qspi_slave(s) container_of(s, struct qspi_slave, slave)\n" - "+\n" - "+struct qspi_regs {\n" - "+\tu32 pid;\n" - "+\tu32 pad0[3];\n" - "+\tu32 sysconfig;\n" - "+\tu32 pad1[3];\n" - "+\tu32 intr_status_raw_set;\n" - "+\tu32 intr_status_enabled_clear;\n" - "+\tu32 intr_enable_set;\n" - "+\tu32 intr_enable_clear;\n" - "+\tu32 intc_eoi;\n" - "+\tu32 pad2[3];\n" - "+\tu32 spi_clock_cntrl;\n" - "+\tu32 spi_dc;\n" - "+\tu32 spi_cmd;\n" - "+\tu32 spi_status;\n" - "+\tu32 spi_data;\n" - "+\tu32 spi_setup0;\n" - "+\tu32 spi_setup1;\n" - "+\tu32 spi_setup2;\n" - "+\tu32 spi_setup3;\n" - "+\tu32 spi_switch;\n" - "+\tu32 spi_data1;\n" - "+\tu32 spi_data2;\n" - "+\tu32 spi_data3;\n" - "+};\n" - "+\n" - "+static struct qspi_regs *qspi = (struct qspi_regs *)QSPI_BASE;\n" - "+\n" - "+#define QSPI_TIMEOUT\t\t\t2000000\n" - "+\n" - "+#define QSPI_FCLK\t\t\t192000000\n" - "+\n" - "+/* Clock Control */\n" - "+#define QSPI_CLK_EN\t\t\t(1 << 31)\n" - "+#define QSPI_CLK_DIV_MAX\t\t0xffff\n" - "+\n" - "+/* Command */\n" - "+#define QSPI_EN_CS(n)\t\t\t(n << 28)\n" - "+#define QSPI_WLEN(n)\t\t\t((n-1) << 19)\n" - "+#define QSPI_3_PIN\t\t\t(1 << 18)\n" - "+#define QSPI_RD_SNGL\t\t\t(1 << 16)\n" - "+#define QSPI_WR_SNGL\t\t\t(2 << 16)\n" - "+#define QSPI_INVAL\t\t\t(4 << 16)\n" - "+\n" - "+/* Device Control */\n" - "+#define QSPI_DD(m, n)\t\t\t(m << (3 + n*8))\n" - "+#define QSPI_CKPHA(n)\t\t\t(1 << (2 + n*8))\n" - "+#define QSPI_CSPOL(n)\t\t\t(1 << (1 + n*8))\n" - "+#define QSPI_CKPOL(n)\t\t\t(1 << (n*8))\n" - "+\n" - "+/* Status */\n" - "+#define QSPI_WC\t\t\t\t(1 << 1)\n" - "+#define QSPI_BUSY\t\t\t(1 << 0)\n" - "+#define QSPI_WC_BUSY\t\t\t(QSPI_WC | QSPI_BUSY)\n" - "+#define QSPI_XFER_DONE\t\t\tQSPI_WC\n" - "+\n" - "+int spi_cs_is_valid(unsigned int bus, unsigned int cs)\n" - "+{\n" - "+\treturn 1;\n" - "+}\n" - "+\n" - "+void spi_cs_activate(struct spi_slave *slave)\n" - "+{\n" - "+\t/* CS handled in xfer */\n" - "+\treturn;\n" - "+}\n" - "+\n" - "+void spi_cs_deactivate(struct spi_slave *slave)\n" - "+{\n" - "+\t/* CS handled in xfer */\n" - "+\treturn;\n" - "+}\n" - "+\n" - "+void spi_init(void)\n" - "+{\n" - "+\t/* nothing to do */\n" - "+}\n" - "+\n" - "+void spi_set_speed(struct spi_slave *slave, uint hz)\n" - "+{\n" - "+\tuint clk_div;\n" - "+\n" - "+\tif (!hz)\n" - "+\t\tclk_div = 0;\n" - "+\telse\n" - "+\t\tclk_div = (QSPI_FCLK / hz) - 1;\n" - "+\n" - "+\tdebug(\"%s: hz: %d, clock divider %d\\n\", __func__, hz, clk_div);\n" - "+\n" - "+\t/* disable SCLK */\n" - "+\twritel(readl(&qspi->spi_clock_cntrl) & ~QSPI_CLK_EN, &qspi->spi_clock_cntrl);\n" - "+\n" - "+\tif (clk_div < 0) {\n" - "+\t\tdebug(\"%s: clock divider < 0, using /1 divider\\n\", __func__);\n" - "+\t\tclk_div = 0;\n" - "+\t}\n" - "+\n" - "+\tif (clk_div > QSPI_CLK_DIV_MAX) {\n" - "+\t\tdebug(\"%s: clock divider >%d , using /%d divider\\n\",\n" - "+\t\t\t__func__, QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);\n" - "+\t\tclk_div = QSPI_CLK_DIV_MAX;\n" - "+\t}\n" - "+\n" - "+\t/* enable SCLK */\n" - "+\twritel(QSPI_CLK_EN | clk_div, &qspi->spi_clock_cntrl);\n" - "+\tdebug(\"%s: spi_clock_cntrl %08x\\n\", __func__, readl(&qspi->spi_clock_cntrl));\n" - "+}\n" - "+\n" - "+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,\n" - "+\t\t\t\t unsigned int max_hz, unsigned int mode)\n" - "+{\n" - "+\tstruct qspi_slave *qslave;\n" - "+\n" - "+\tqslave = spi_alloc_slave(struct qspi_slave, bus, cs);\n" - "+\tif (!qslave)\n" - "+\t\treturn NULL;\n" - "+\n" - "+\tspi_set_speed(&qslave->slave, max_hz);\n" - "+\tqslave->mode = mode;\n" - "+\tdebug(\"%s: bus:%i cs:%i mode:%i\\n\", __func__, bus, cs, mode);\n" - "+\n" - "+\treturn &qslave->slave;\n" - "+}\n" - "+\n" - "+void spi_free_slave(struct spi_slave *slave)\n" - "+{\n" - "+\tstruct qspi_slave *qslave = to_qspi_slave(slave);\n" - "+\tfree(qslave);\n" - "+}\n" - "+\n" - "+int spi_claim_bus(struct spi_slave *slave)\n" - "+{\n" - "+\tdebug(\"%s: bus:%i cs:%i\\n\", __func__, slave->bus, slave->cs);\n" - "+\n" - "+\twritel(0, &qspi->spi_dc);\n" - "+\twritel(0, &qspi->spi_cmd);\n" - "+\twritel(0, &qspi->spi_data);\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+void spi_release_bus(struct spi_slave *slave)\n" - "+{\n" - "+\tdebug(\"%s: bus:%i cs:%i\\n\", __func__, slave->bus, slave->cs);\n" - "+\n" - "+\twritel(0, &qspi->spi_dc);\n" - "+\twritel(0, &qspi->spi_cmd);\n" - "+\twritel(0, &qspi->spi_data);\n" - "+}\n" - "+\n" - "+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,\n" - "+\t void *din, unsigned long flags)\n" - "+{\n" - "+\tstruct qspi_slave *qslave = to_qspi_slave(slave);\n" - "+\tuint words = bitlen >> 3; /* fixed 8-bit word length */\n" - "+\tconst uchar *txp = dout;\n" - "+\tuchar *rxp = din;\n" - "+\tuint status;\n" - "+\tint timeout;\n" - "+\n" - "+\tdebug(\"%s: bus:%i cs:%i bitlen:%i words:%i flags:%lx\\n\", __func__,\n" - "+\t\tslave->bus, slave->cs, bitlen, words, flags);\n" - "+\tif (bitlen == 0)\n" - "+\t\treturn -1;\n" - "+\n" - "+\tif (bitlen % 8) {\n" - "+\t\tflags |= SPI_XFER_END;\n" - "+\t\treturn -1;\n" - "+\t}\n" - "+\n" - "+\t/* setup command reg */\n" - "+\tqslave->cmd = 0;\n" - "+\tqslave->cmd |= QSPI_WLEN(8);\n" - "+\tqslave->cmd |= QSPI_EN_CS(slave->cs);\n" - "+\tif (flags & SPI_3WIRE)\n" - "+\t\tqslave->cmd |= QSPI_3_PIN;\n" - "+\tqslave->cmd |= 0xfff;\n" - "+\n" - "+\t/* setup device control reg */\n" - "+\tqslave->dc = 0;\n" - "+\tif (qslave->mode & SPI_CPHA)\n" - "+\t\tqslave->dc |= QSPI_CKPHA(slave->cs);\n" - "+\tif (qslave->mode & SPI_CPOL)\n" - "+\t\tqslave->dc |= QSPI_CKPOL(slave->cs);\n" - "+\tif (qslave->mode & SPI_CS_HIGH)\n" - "+\t\tqslave->dc |= QSPI_CSPOL(slave->cs);\n" - "+\n" - "+\twhile (words--) {\n" - "+\t\tif (txp) {\n" - "+\t\t\tdebug(\"tx cmd %08x dc %08x data %02x\\n\",\n" - "+\t\t\t qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp);\n" - "+\t\t\twritel(*txp++, &qspi->spi_data);\n" - "+\t\t\twritel(qslave->dc, &qspi->spi_dc);\n" - "+\t\t\twritel(qslave->cmd | QSPI_WR_SNGL, &qspi->spi_cmd);\n" - "+\t\t\tstatus = readl(&qspi->spi_status);\n" - "+\t\t\ttimeout = QSPI_TIMEOUT;\n" - "+\t\t\twhile ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {\n" - "+\t\t\t\tif (--timeout < 0) {\n" - "+\t\t\t\t\tprintf(\"QSPI tx timed out\\n\");\n" - "+\t\t\t\t\treturn -1;\n" - "+\t\t\t\t}\n" - "+\t\t\t\tstatus = readl(&qspi->spi_status);\n" - "+\t\t\t}\n" - "+\t\t\tdebug(\"tx done, status %08x\\n\", status);\n" - "+\t\t}\n" - "+\t\tif (rxp) {\n" - "+\t\t\tdebug(\"rx cmd %08x dc %08x\\n\",\n" - "+\t\t\t qslave->cmd | QSPI_RD_SNGL, qslave->dc);\n" - "+\t\t\twritel(qslave->dc, &qspi->spi_dc);\n" - "+\t\t\twritel(qslave->cmd | QSPI_RD_SNGL, &qspi->spi_cmd);\n" - "+\t\t\tstatus = readl(&qspi->spi_status);\n" - "+\t\t\ttimeout = QSPI_TIMEOUT;\n" - "+\t\t\twhile ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {\n" - "+\t\t\t\tif (--timeout < 0) {\n" - "+\t\t\t\t\tprintf(\"QSPI rx timed out\\n\");\n" - "+\t\t\t\t\treturn -1;\n" - "+\t\t\t\t}\n" - "+\t\t\t\tstatus = readl(&qspi->spi_status);\n" - "+\t\t\t}\n" - "+\t\t\t*rxp++ = readl(&qspi->spi_data);\n" - "+\t\t\tdebug(\"rx done, status %08x, read %02x\\n\",\n" - "+\t\t\t status, *(rxp-1));\n" - "+\t\t}\n" - "+\t}\n" - "+\n" - "+\t/* Terminate frame */\n" - "+\tif (flags & SPI_XFER_END)\n" - "+\t\twritel(qslave->cmd | QSPI_INVAL, &qspi->spi_cmd);\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "-- \n" - 1.7.1 - "\01:4\0" - "fn\00003-dra7xx_evm-add-SPL-API-QSPI-and-serial-flash-support.patch\0" - "b\0" - ">From 89b1ad9848df89817dc8bac7ea12a71d811921ce Mon Sep 17 00:00:00 2001\n" - "From: Matt Porter <mporter@ti.com>\n" - "Date: Mon, 6 May 2013 15:33:19 -0400\n" - "Subject: [PATCH 3/5] dra7xx_evm: add SPL API, QSPI, and serial flash support\n" - "\n" - "Enables support for SPI SPL, QSPI and Spansion serial flash device\n" - "on the EVM. Configures pin muxes for QSPI mode.\n" - "\n" - "Signed-off-by: Matt Porter <mporter@ti.com>\n" - "Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>\n" - "---\n" - " board/ti/dra7xx/mux_data.h | 10 ++++++++++\n" - " include/configs/dra7xx_evm.h | 17 +++++++++++++++++\n" - " 2 files changed, 27 insertions(+), 0 deletions(-)\n" - "\n" - "diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h\n" - "index 5a91966..b26a9be 100644\n" - "--- a/board/ti/dra7xx/mux_data.h\n" - "+++ b/board/ti/dra7xx/mux_data.h\n" - "@@ -53,6 +53,16 @@ const struct pad_conf_entry core_padconf_array_essential[] = {\n" - " \t{UART1_RTSN, (IEN | PTU | PDIS | M3)},\n" - " \t{I2C1_SDA, (IEN | PTU | PDIS | M0)},\n" - " \t{I2C1_SCL, (IEN | PTU | PDIS | M0)},\n" - "+\t{GPMC_A13, (PTU | IEN | M1)},\t/* QSPI1_RTCLK */\n" - "+\t{GPMC_A18, (PTU | IEN | M1)},\t/* QSPI1_SCLK */\n" - "+\t{GPMC_A17, (PTU | IEN | M1)},\t/* QSPI1_D[0] */\n" - "+\t{GPMC_A16, (PTU | IEN | M1)},\t/* QSPI1_D[1] */\n" - "+\t{GPMC_A15, (PTU | IEN | M1)},\t/* QSPI1_D[2] */\n" - "+\t{GPMC_A14, (PTU | IEN | M1)},\t/* QSPI1_D[3] */\n" - "+\t{GPMC_CS2, (PTU | M1)},\t\t/* QSPI1_CS[0] */\n" - "+\t{GPMC_CS3, (PTU | M1)},\t\t/* QSPI1_CS[1] */\n" - "+\t{GPMC_A3, (PTU | M1)},\t\t/* QSPI1_CS[2] */\n" - "+\t{GPMC_A4, (PTU | M1)},\t\t/* QSPI1_CS[3] */\n" - " };\n" - " \n" - " const struct pad_conf_entry core_padconf_array_non_essential[] = {\n" - "diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h\n" - "index 2518352..3671e45 100644\n" - "--- a/include/configs/dra7xx_evm.h\n" - "+++ b/include/configs/dra7xx_evm.h\n" - "@@ -56,4 +56,21 @@\n" - " \n" - " #define EMIF1_EMIF2\n" - " \n" - "+/* SPI */\n" - "+#define CONFIG_TI_QSPI\n" - "+#define CONFIG_SPI_FLASH\n" - "+#define CONFIG_SPI_FLASH_SPANSION\n" - "+#define CONFIG_CMD_SF\n" - "+#define CONFIG_CMD_SPI\n" - "+#define CONFIG_SF_DEFAULT_SPEED\t\t12000000\n" - "+#define CONFIG_DEFAULT_SPI_MODE\t\tSPI_MODE_3\n" - "+\n" - "+/* SPI SPL */\n" - "+#define CONFIG_SPL_SPI_SUPPORT\n" - "+#define CONFIG_SPL_SPI_LOAD\n" - "+#define CONFIG_SPL_SPI_FLASH_SUPPORT\n" - "+#define CONFIG_SPL_SPI_BUS\t\t0\n" - "+#define CONFIG_SPL_SPI_CS\t\t0\n" - "+#define CONFIG_SYS_SPI_U_BOOT_OFFS\t0x20000\n" - "+\n" - " #endif /* __CONFIG_DRA7XX_EVM_H */\n" - "-- \n" - 1.7.1 - "\01:5\0" - "fn\00004-drivers-mtd-spi-Modify-read-write-command-for-sfl256.patch\0" - "b\0" - ">From e4139e66b956d17a9157a7b6d055e9f8c585041d Mon Sep 17 00:00:00 2001\n" - "From: Sourav Poddar <sourav.poddar@ti.com>\n" - "Date: Fri, 7 Jun 2013 17:15:36 +0530\n" - "Subject: [PATCH 4/5] drivers: mtd: spi: Modify read/write command for sfl256s flash.\n" - "\n" - "Reading using the already supported read command is causing regression\n" - "even while reading 4k bytes, as a result doing a page by page read.\n" - "\n" - "At the end of the write sequence, write enable latch should be disabled and\n" - "re enabled while doing the next page programming.\n" - "\n" - "Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>\n" - "---\n" - " drivers/mtd/spi/spi_flash.c | 39 ++++++++++++++++++++++++++++++++++-----\n" - " 1 files changed, 34 insertions(+), 5 deletions(-)\n" - "\n" - "diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c\n" - "index 111185a..8c3a2cf 100644\n" - "--- a/drivers/mtd/spi/spi_flash.c\n" - "+++ b/drivers/mtd/spi/spi_flash.c\n" - "@@ -117,6 +117,12 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,\n" - " \t\tif (ret)\n" - " \t\t\tbreak;\n" - " \n" - "+\t\tret = spi_flash_cmd_write_disable(flash);\n" - "+\t\tif (ret < 0) {\n" - "+\t\t\tprintf(\"SF: disabling write failed\\n\");\n" - "+\t\t\tbreak;\n" - "+\t\t}\n" - "+\n" - " \t\tbyte_addr += chunk_len;\n" - " \t\tif (byte_addr == page_size) {\n" - " \t\t\tpage_addr++;\n" - "@@ -147,17 +153,40 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,\n" - " int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,\n" - " \t\tsize_t len, void *data)\n" - " {\n" - "-\tu8 cmd[5];\n" - "+\tunsigned long page_addr, byte_addr, page_size;\n" - "+\tsize_t chunk_len, actual;\n" - "+\tint ret = 0;\n" - "+\tu8 cmd[4];\n" - " \n" - " \t/* Handle memory-mapped SPI */\n" - " \tif (flash->memory_map)\n" - " \t\tmemcpy(data, flash->memory_map + offset, len);\n" - "+\tpage_size = flash->page_size;\n" - "+\tpage_addr = offset / page_size;\n" - "+\tbyte_addr = offset % page_size;\n" - "+\n" - "+\tcmd[0] = CMD_READ_ARRAY_SLOW;\n" - "+\tfor (actual = 0; actual < len; actual += chunk_len) {\n" - "+\t\tchunk_len = min(len - actual, page_size - byte_addr);\n" - "+\n" - "+\t\tcmd[1] = page_addr >> 8;\n" - "+\t\tcmd[2] = page_addr;\n" - "+\t\tcmd[3] = byte_addr;\n" - "+\n" - "+\t\tret = spi_flash_read_common(flash, cmd, sizeof(cmd), data + actual, chunk_len);\n" - "+\t\tif (ret < 0) {\n" - "+\t\t\tdebug(\"SF: read failed\");\n" - "+\t\t\tbreak;\n" - "+\t\t}\n" - " \n" - "-\tcmd[0] = CMD_READ_ARRAY_FAST;\n" - "-\tspi_flash_addr(offset, cmd);\n" - "-\tcmd[4] = 0x00;\n" - "+\t\tbyte_addr += chunk_len;\n" - "+\t\tif (byte_addr == page_size) {\n" - "+\t\t\tpage_addr++;\n" - "+\t\t\tbyte_addr = 0;\n" - "+\t\t}\n" - "+\t}\n" - " \n" - "-\treturn spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);\n" - "+\treturn ret;\n" - " }\n" - " \n" - " int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,\n" - "-- \n" - 1.7.1 -02b8540940334c37a9d219c645738833a35ea7fe6f6a8f06244f493a466f7743 +aae8ca155ae83cf63b14e65ae4e1bb4ee55134611dcd3bfc42c7df8d40a6d027
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.