From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51340) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Usv9O-0002p6-JT for qemu-devel@nongnu.org; Sat, 29 Jun 2013 09:25:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Usv9M-0002PV-1S for qemu-devel@nongnu.org; Sat, 29 Jun 2013 09:25:14 -0400 Received: from cantor2.suse.de ([195.135.220.15]:47880 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Usv9L-0002P8-Oc for qemu-devel@nongnu.org; Sat, 29 Jun 2013 09:25:11 -0400 Message-ID: <51CEE030.70904@suse.de> Date: Sat, 29 Jun 2013 15:25:04 +0200 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1372420798-4790-1-git-send-email-andre.przywara@calxeda.com> <51CED912.4080905@suse.de> In-Reply-To: <51CED912.4080905@suse.de> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] highbank: add initial Calxeda Midway A15 support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andre Przywara Cc: Peter Maydell , aliguori@us.ibm.com, Mitsyanko Igor , qemu-devel@nongnu.org, Rob Herring Am 29.06.2013 14:54, schrieb Andreas F=E4rber: > Am 28.06.2013 13:59, schrieb Andre Przywara: >> From: Rob Herring >> >> While the Calxeda Midway part is actually a bit more than a "Highbank >> with A15s", for QEMU's purposes this view is sufficient. So to allow >> both emulation with that chip as well as KVM guests using that model >> add an A15 CPU and it's peripherals as an option. The use of: >> "-M highbank -cpu cortex-a15" simply gives the new chip without the >> need for a new model. >> >> Signed-off-by: Rob Herring >> Signed-off-by: Andre Przywara >> --- >> hw/arm/highbank.c | 19 +++++++++++++------ >> 1 file changed, 13 insertions(+), 6 deletions(-) >> >> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c >> index 4405dbd..ed864c6 100644 >> --- a/hw/arm/highbank.c >> +++ b/hw/arm/highbank.c >> @@ -196,6 +196,7 @@ static void highbank_init(QEMUMachineInitArgs *arg= s) >> const char *kernel_filename =3D args->kernel_filename; >> const char *kernel_cmdline =3D args->kernel_cmdline; >> const char *initrd_filename =3D args->initrd_filename; >> + CPUARMState *env =3D NULL; >> DeviceState *dev; >> SysBusDevice *busdev; >> qemu_irq *irqp; >> @@ -223,6 +224,8 @@ static void highbank_init(QEMUMachineInitArgs *arg= s) >> cpu->reset_cbar =3D GIC_BASE_ADDR; >> irqp =3D arm_pic_init_cpu(cpu); >> cpu_irq[n] =3D irqp[ARM_PIC_CPU_IRQ]; >> + >> + env =3D &cpu->env; >> } >> =20 >> sysmem =3D get_system_memory(); >> @@ -246,7 +249,16 @@ static void highbank_init(QEMUMachineInitArgs *ar= gs) >> } >> } >> =20 >> - dev =3D qdev_create(NULL, "a9mpcore_priv"); >> + if (arm_feature(env, ARM_FEATURE_LPAE)) { >> + dev =3D qdev_create(NULL, "a15mpcore_priv"); >=20 > This feels a bit fragile to me... Cortex-A7 or other cores might grow > support for LPAE, too. Add to that, feature inference is done as part of QOM realize, for which it is too early to depend on in machine init. > I would suggest something along these lines: >=20 > if (object_get_class(OBJECT(cpu)) =3D=3D object_class_by_name("cortex-a= 15-" > TYPE_ARM_CPU)) {...} Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg