From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE) Date: Mon, 1 Jul 2013 10:44:11 +0100 Message-ID: <51D14F6B.3090307@citrix.com> References: <51D16A2102000078000E1E36@nat28.tlf.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <51D16A2102000078000E1E36@nat28.tlf.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: Cyclonus J , xen-devel List-Id: xen-devel@lists.xenproject.org On 01/07/13 10:38, Jan Beulich wrote: >>>> On 28.06.13 at 23:02, Cyclonus J wrote: >> I am wondering if we can disable the VMX interception for >> MSR_SHADOW_GS_BASE as AMD is already doing that. > I can't immediately see any reason why we shouldn't be permitted > to do this, but I also don't think this should be performance critical. > > If you feel this is important, why don't you contribute a patch, > with its description saying under what conditions this can yield > measurable benefit? > > Jan Will this not cause a VMexit on each swapgs instruction, as the instruction itself does write to MSR 0xC0000102? I have looked quite closely through the Intel manuals and cant find confirmation one way or another. ~Andrew > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xen.org > http://lists.xen.org/xen-devel