From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Keir Fraser <keir.xen@gmail.com>
Cc: Cyclonus J <cyclonusj@gmail.com>, Jan Beulich <JBeulich@suse.com>,
xen-devel <xen-devel@lists.xen.org>
Subject: Re: vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE)
Date: Mon, 1 Jul 2013 11:00:12 +0100 [thread overview]
Message-ID: <51D1532C.5030907@citrix.com> (raw)
In-Reply-To: <CDF70FC0.2B42B%keir.xen@gmail.com>
On 01/07/13 10:51, Keir Fraser wrote:
> On 01/07/2013 10:44, "Andrew Cooper" <andrew.cooper3@citrix.com> wrote:
>
>> On 01/07/13 10:38, Jan Beulich wrote:
>>>>>> On 28.06.13 at 23:02, Cyclonus J <cyclonusj@gmail.com> wrote:
>>>> I am wondering if we can disable the VMX interception for
>>>> MSR_SHADOW_GS_BASE as AMD is already doing that.
>>> I can't immediately see any reason why we shouldn't be permitted
>>> to do this, but I also don't think this should be performance critical.
>>>
>>> If you feel this is important, why don't you contribute a patch,
>>> with its description saying under what conditions this can yield
>>> measurable benefit?
>>>
>>> Jan
>> Will this not cause a VMexit on each swapgs instruction, as the
>> instruction itself does write to MSR 0xC0000102?
>>
>> I have looked quite closely through the Intel manuals and cant find
>> confirmation one way or another.
> Only RDMSR/WRMSR trap on the MSR bitmaps.
Ok - so the performance aspect depends on whether the guest is using
per-thread kernel areas or not, in combination with swapgs.
I would have thought that this would be a sensible change to make at the
start of 4.4
~Andrew
prev parent reply other threads:[~2013-07-01 10:00 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-28 21:02 vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE) Cyclonus J
2013-07-01 9:38 ` Jan Beulich
2013-07-01 9:44 ` Andrew Cooper
2013-07-01 9:48 ` Jan Beulich
2013-07-01 9:51 ` Keir Fraser
2013-07-01 10:00 ` Andrew Cooper [this message]
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