[U-Boot] [PATCH 4/8] arm kirkwood add MVSDIO driver v3

[DrEagle <dreagle@doukki.net>]

    - add kirkwood MVSDIO driver

    WIP : MVSDIO v3
    WIP : MVSDIO SD/MMC Driver Support for Marvell Kirkwood SoC need debugging and code cleaning
    
    Fix SDIO/MMC driver
    - MVSDIO driver now works in non DEBUG mode
    
    Change from v2:
    - add base_clock in mrvl_mmc_initialize and mrvl_mmc_set_clk
      check kirkwood device and revision to fix clock rates
    - add kirkwood supported devices and revisions
    - add sheevaplug board_mmc_init
    - MVSDIO driver code mostly rewrote and still need some cleaning

    Change from v1:
    - Fix an issue with most SDHC cards because of timeout delay
    
    Signed-off-by: drEagle <uboot@doukki.net>

 drivers/mmc/Makefile                           |
 drivers/mmc/mrvl_mmc.c                         |
 include/mrvl_mmc.h                             |

diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 1d6faa2..2a2745d 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -37,6 +37,7 @@ COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
 COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
 COBJS-$(CONFIG_MMC_SPI) += mmc_spi.o
 COBJS-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
+COBJS-$(CONFIG_MRVL_MMC) += mrvl_mmc.o
 COBJS-$(CONFIG_MV_SDHCI) += mv_sdhci.o
 COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
 COBJS-$(CONFIG_MXS_MMC) += mxsmmc.o
diff --git a/drivers/mmc/mrvl_mmc.c b/drivers/mmc/mrvl_mmc.c
new file mode 100644
index 0000000..b0571cf
--- /dev/null
+++ b/drivers/mmc/mrvl_mmc.c
@@ -0,0 +1,446 @@
+/*
+ * Driver for Marvell SDIO/MMC controller
+ *
+ * (C) Copyright 2012
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: G?rald Kerma <uboot@doukki.net>
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <part.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+
+#include <mrvl_mmc.h>
+
+#define DRIVER_NAME	"mvsdio"
+
+static int maxfreq = MRVL_MMC_CLOCKRATE_MAX;
+
+#define mvsd_write(offs, val)	writel(val, CONFIG_SYS_MMC_BASE + (offs))
+#define mvsd_read(offs)			readl(CONFIG_SYS_MMC_BASE + (offs))
+
+#define MRVL_MMC_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
+
+static int mrvl_mmc_setup_data(struct mmc_data *data)
+{
+	u32 ctrl_reg;
+
+#ifdef DEBUG
+	printf("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME,
+		(data->flags & MMC_DATA_READ) ? "read" : "write",
+		data->blocks, data->blocksize);
+#endif
+
+	/* default to maximum timeout */
+	ctrl_reg = mvsd_read(SDIO_HOST_CTRL);
+	ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
+	mvsd_write(SDIO_HOST_CTRL, ctrl_reg);
+
+	if (data->flags & MMC_DATA_READ) {
+		mvsd_write(SDIO_SYS_ADDR_LOW,(u32)data->dest & 0xffff);
+		mvsd_write(SDIO_SYS_ADDR_HI,(u32)data->dest >> 16);
+	} else {
+		mvsd_write(SDIO_SYS_ADDR_LOW,(u32)data->src & 0xffff);
+		mvsd_write(SDIO_SYS_ADDR_HI,(u32)data->src >> 16);
+	}
+
+	mvsd_write(SDIO_BLK_COUNT, data->blocks);
+	mvsd_write(SDIO_BLK_SIZE, data->blocksize);
+
+	return 0;
+}
+
+static int mrvl_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+{
+	int	timeout = 10;
+	ushort waittype = 0;
+	ushort resptype = 0;
+	ushort xfertype = 0;
+	ushort resp_indx = 0;
+
+#ifdef CONFIG_MMC_DEBUG
+	printf("cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n", cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
+#endif
+
+	udelay(10*1000);
+
+#ifdef CONFIG_MMC_DEBUG
+	printf("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,
+		cmd->cmdidx, mvsd_read(SDIO_HW_STATE));
+#endif
+
+	/* Checking if card is busy */
+	while ((mvsd_read(SDIO_HW_STATE) & CARD_BUSY)) {
+		if (timeout == 0) {
+			printf("%s: card busy!\n", DRIVER_NAME);
+			return -1;
+		}
+		timeout--;
+		udelay(1000);
+	}
+
+	/* Set up for a data transfer if we have one */
+	if (data) {
+		int err = mrvl_mmc_setup_data(data);
+		if (err)
+			return err;
+	}
+
+	resptype = SDIO_CMD_INDEX(cmd->cmdidx);
+
+	/* Analyzing resptype/xfertype/waittype for the command */
+	if (cmd->resp_type & MMC_RSP_BUSY)
+		resptype |= SDIO_CMD_RSP_48BUSY;
+	else if (cmd->resp_type & MMC_RSP_136)
+		resptype |= SDIO_CMD_RSP_136;
+	else if (cmd->resp_type & MMC_RSP_PRESENT)
+		resptype |= SDIO_CMD_RSP_48;
+	else
+		resptype |= SDIO_CMD_RSP_NONE;
+
+	if (cmd->resp_type & MMC_RSP_CRC)
+		resptype |= SDIO_CMD_CHECK_CMDCRC;
+
+	if (cmd->resp_type & MMC_RSP_OPCODE)
+		resptype |= SDIO_CMD_INDX_CHECK;
+
+	if (cmd->resp_type & MMC_RSP_PRESENT) {
+		resptype |= SDIO_UNEXPECTED_RESP;
+		waittype |= SDIO_NOR_UNEXP_RSP;
+	}
+
+	if (data) {
+		resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
+		xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
+		if (data->flags & MMC_DATA_READ) {
+			xfertype |= SDIO_XFER_MODE_TO_HOST;
+			waittype = SDIO_NOR_DMA_INI;
+		} else
+			waittype |= SDIO_NOR_XFER_DONE;
+	} else {
+		waittype |= SDIO_NOR_CMD_DONE;
+	}
+
+	/* Setting cmd arguments */
+	mvsd_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
+	mvsd_write(SDIO_ARG_HI, cmd->cmdarg >> 16 );
+
+	/* Setting Xfer mode */
+	mvsd_write(SDIO_XFER_MODE, xfertype);
+
+	mvsd_write(SDIO_NOR_INTR_STATUS, ~SDIO_NOR_CARD_INT);
+	mvsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
+
+	/* Sending command */
+	mvsd_write(SDIO_CMD, resptype);
+/*
+	mvsd_write(SDIO_CMD, MRVL_MMC_MAKE_CMD(cmd->cmdidx, resptype));
+*/
+
+	mvsd_write(SDIO_NOR_INTR_EN, SDIO_POLL_MASK);
+	mvsd_write(SDIO_ERR_INTR_EN, SDIO_POLL_MASK);
+
+	/* Waiting for completion */
+	timeout = 1000000;
+
+	while (!((mvsd_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
+		if (mvsd_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
+#ifdef DEBUG
+			printf("%s: mrvl_mmc_send_cmd: error! cmdidx : %d, err reg: %04x\n", DRIVER_NAME, cmd->cmdidx, mvsd_read(SDIO_ERR_INTR_STATUS));
+#endif
+			if (mvsd_read(SDIO_ERR_INTR_STATUS) & (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
+				return TIMEOUT;
+			return COMM_ERR;
+		}
+
+		timeout--;
+		udelay(1);
+		if (timeout <= 0) {
+			printf("%s: command timed out\n", DRIVER_NAME);
+			return TIMEOUT;
+		}
+	}
+
+	/* Handling response */
+	if (cmd->resp_type & MMC_RSP_136) {
+		uint response[8];
+		for (resp_indx = 0; resp_indx < 8; resp_indx++)
+			response[resp_indx] = mvsd_read(SDIO_RSP(resp_indx));
+
+		cmd->response[0] =		((response[0] & 0x03ff) << 22) |
+								((response[1] & 0xffff) << 6) |
+								((response[2] & 0xfc00) >> 10);
+		cmd->response[1] =		((response[2] & 0x03ff) << 22) |
+								((response[3] & 0xffff) << 6) |
+								((response[4] & 0xfc00) >> 10);
+		cmd->response[2] =		((response[4] & 0x03ff) << 22) |
+								((response[5] & 0xffff) << 6) |
+								((response[6] & 0xfc00) >> 10);
+		cmd->response[3] =		((response[6] & 0x03ff) << 22) |
+								((response[7] & 0x3fff) << 8);
+	} else if (cmd->resp_type & MMC_RSP_PRESENT) {
+		uint response[3];
+		for (resp_indx = 0; resp_indx < 3; resp_indx++)
+			response[resp_indx] = mvsd_read(SDIO_RSP(resp_indx));
+
+		cmd->response[0] = 		((response[2] & 0x003f) << (8 - 8))		|
+								((response[1] & 0xffff) << (14 - 8))	|
+								((response[0] & 0x03ff) << (30 - 8));
+		cmd->response[1] = 		((response[0] & 0xfc00) >> 10);
+		cmd->response[2] =		0;
+		cmd->response[3] =		0;
+	}
+
+#ifdef CONFIG_MMC_DEBUG
+	printf("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
+	printf("[0x%x] ", cmd->response[0]);
+	printf("[0x%x] ", cmd->response[1]);
+	printf("[0x%x] ", cmd->response[2]);
+	printf("[0x%x] ", cmd->response[3]);
+	printf("\n");
+#endif
+
+	return 0;
+}
+
+static void mvsd_power_up(void)
+{
+#ifdef DEBUG
+	printf("%s: power up\n", DRIVER_NAME);
+#endif
+	/* disable interrupts */
+	mvsd_write(SDIO_NOR_INTR_EN, 0);
+	mvsd_write(SDIO_ERR_INTR_EN, 0);
+
+	/* SW reset */
+	mvsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
+
+	mvsd_write(SDIO_XFER_MODE, 0);
+
+	/* enable status */
+	mvsd_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
+	mvsd_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
+
+	/* enable interrupts status */
+	mvsd_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
+	mvsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
+}
+
+static void mvsd_power_down(void)
+{
+#ifdef DEBUG
+	printf("%s: power down\n", DRIVER_NAME);
+#endif
+	/* disable interrupts */
+	mvsd_write(SDIO_NOR_INTR_EN, 0);
+	mvsd_write(SDIO_ERR_INTR_EN, 0);
+
+	/* SW reset */
+	mvsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
+
+	mvsd_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
+
+	/* disable status */
+	mvsd_write(SDIO_NOR_STATUS_EN, 0);
+	mvsd_write(SDIO_ERR_STATUS_EN, 0);
+
+	/* enable interrupts status */
+	mvsd_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
+	mvsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
+}
+
+static u32 mrvl_mmc_get_base_clock(void)
+{
+	u32 devid;
+	u32 revid;
+
+	if (0) {
+		kirkwood_pcie_id(&devid, &revid);
+
+#ifdef DEBUG
+		printf("%s: board devid[0x%x] devid[0x%x]\n", DRIVER_NAME, devid, revid);
+#endif
+
+		if (revid == 0 && devid != MV88F6282_DEV_ID){
+	 /* catch all Kirkwood Z0's */
+#ifdef DEBUG
+			printf("%s: Kirkwood Z0's base clock = %d\n", DRIVER_NAME, MRVL_MMC_BASE_FAST_CLK_100);
+#endif
+			return MRVL_MMC_BASE_FAST_CLK_100;
+		}else{
+#ifdef DEBUG
+			printf("%s: base clock = %d\n", DRIVER_NAME, MRVL_MMC_BASE_FAST_CLK_200);
+#endif
+			return MRVL_MMC_BASE_FAST_CLK_200;
+		}
+	}
+	return MRVL_MMC_BASE_FAST_CLOCK;
+}
+
+static void mrvl_mmc_set_clk(unsigned int clock)
+{
+	unsigned int m;
+
+	if (clock == 0){
+#ifdef DEBUG
+		printf("%s: clock off\n", DRIVER_NAME);
+#endif
+		mvsd_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
+		mvsd_write(SDIO_CLK_DIV, MRVL_MMC_BASE_DIV_MAX);
+	}else{
+		m = MRVL_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
+		if (m > MRVL_MMC_BASE_DIV_MAX)
+			m = MRVL_MMC_BASE_DIV_MAX;
+#ifdef DEBUG
+		printf("%s: mrvl_mmc_set_clk: base = %d dividor = 0x%x clock=%d\n", DRIVER_NAME, mrvl_mmc_get_base_clock(), m, clock);
+#endif
+		mvsd_write(SDIO_CLK_DIV, m & MRVL_MMC_BASE_DIV_MAX);
+	}
+	udelay(10*1000);
+}
+
+static void mrvl_mmc_set_bus(unsigned int bus)
+{
+	u32 ctrl_reg = 0;
+
+	ctrl_reg = mvsd_read(SDIO_HOST_CTRL);
+	ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
+
+	switch (bus) {
+		case 4:
+			ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
+			break;
+		case 1:
+		default:
+			ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
+	}
+	/* default transfer mode */
+	ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
+	ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
+
+	/* default to maximum timeout */
+	ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
+
+	ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
+
+	ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
+
+	/*
+	 * The HI_SPEED_EN bit is causing trouble with many (but not all)
+	 * high speed SD, SDHC and SDIO cards.  Not enabling that bit
+	 * makes all cards work.  So let's just ignore that bit for now
+	 * and revisit this issue if problems for not enabling this bit
+	 * are ever reported.
+	 */
+#if 0
+	if (ios->timing == MMC_TIMING_MMC_HS ||
+	    ios->timing == MMC_TIMING_SD_HS)
+		ctrl_reg |= SDIO_HOST_CTRL_HI_SPEED_EN;
+#endif
+
+#ifdef DEBUG
+	printf("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg,
+		(ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
+			"push-pull" : "open-drain",
+		(ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
+			"4bit-width" : "1bit-width",
+		(ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
+			"high-speed" : "");
+#endif
+
+	mvsd_write(SDIO_HOST_CTRL, ctrl_reg);
+	udelay(10*1000);
+}
+
+static void mrvl_mmc_set_ios(struct mmc *mmc)
+{
+#ifdef DEBUG
+	printf("%s: bus[%d] clock[%d]\n", DRIVER_NAME, mmc->bus_width, mmc->clock);
+#endif
+	mrvl_mmc_set_bus(mmc->bus_width);
+	mrvl_mmc_set_clk(mmc->clock);
+}
+
+static int mrvl_mmc_init(struct mmc *mmc)
+{
+#ifdef DEBUG
+	printf("%s: mrvl_mmc_init\n", DRIVER_NAME);
+#endif
+
+/*
+ * Setting host parameters
+ * Initial Host Ctrl : Timeout : max , Normal Speed mode, 4-bit data mode
+ * Big Endian, SD memory Card, Push_pull CMD Line
+ */
+	mvsd_write(SDIO_HOST_CTRL,
+		SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
+		SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
+		SDIO_HOST_CTRL_BIG_ENDIAN |
+		SDIO_HOST_CTRL_PUSH_PULL_EN |
+		SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY );
+
+	mvsd_write(SDIO_CLK_CTRL, 0);
+
+	/* enable status */
+	mvsd_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
+	mvsd_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
+
+	/* disable interrupts */
+	mvsd_write(SDIO_NOR_INTR_EN, 0);
+	mvsd_write(SDIO_ERR_INTR_EN, 0);
+
+	/* SW reset */
+	mvsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
+
+	udelay(10*1000);
+	return 0;
+}
+
+int mrvl_mmc_initialize(bd_t *bis)
+{
+	struct mmc *mmc = NULL;
+
+#ifdef DEBUG
+	printf("%s: %s base_clock = %d\n", DRIVER_NAME, kirkwood_id(), mrvl_mmc_get_base_clock());
+#endif
+	mmc = malloc(sizeof(struct mmc));
+	if (!mmc)
+		return -1;
+
+	sprintf(mmc->name, DRIVER_NAME);
+	mmc->send_cmd = mrvl_mmc_send_cmd;
+	mmc->set_ios = mrvl_mmc_set_ios;
+	mmc->init = mrvl_mmc_init;
+	
+	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS;
+
+	mmc->f_min = MRVL_MMC_BASE_FAST_CLOCK/MRVL_MMC_BASE_DIV_MAX;
+	mmc->f_max = maxfreq;
+
+	mmc_register(mmc);
+
+	return 0;
+}
+
diff --git a/include/mrvl_mmc.h b/include/mrvl_mmc.h
new file mode 100644
index 0000000..b5fa91c
--- /dev/null
+++ b/include/mrvl_mmc.h
@@ -0,0 +1,266 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * (C) Copyright 2012
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: G?rald Kerma <uboot@doukki.net>
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MRVL_MMC_H__
+#define __MRVL_MMC_H__
+
+/*
+ * Clock rates
+ */
+
+#define MRVL_MMC_CLOCKRATE_MAX			50000000
+#define MRVL_MMC_BASE_DIV_MAX			0x7ff
+#define MRVL_MMC_BASE_FAST_CLOCK		CONFIG_SYS_TCLK
+#define MRVL_MMC_BASE_FAST_CLK_100		100000000
+#define MRVL_MMC_BASE_FAST_CLK_200		200000000
+
+/* SDIO register */
+#define SDIO_SYS_ADDR_LOW			0x000
+#define SDIO_SYS_ADDR_HI			0x004
+#define SDIO_BLK_SIZE				0x008
+#define SDIO_BLK_COUNT				0x00c
+#define SDIO_ARG_LOW				0x010
+#define SDIO_ARG_HI					0x014
+#define SDIO_XFER_MODE				0x018
+#define SDIO_CMD					0x01c
+#define SDIO_RSP(i)					(0x020 + ((i)<<2))
+#define SDIO_RSP0					0x020
+#define SDIO_RSP1					0x024
+#define SDIO_RSP2					0x028
+#define SDIO_RSP3					0x02c
+#define SDIO_RSP4					0x030
+#define SDIO_RSP5					0x034
+#define SDIO_RSP6					0x038
+#define SDIO_RSP7					0x03c
+#define SDIO_BUF_DATA_PORT			0x040
+#define SDIO_RSVED					0x044
+#define SDIO_HW_STATE				0x048
+#define SDIO_PRESENT_STATE0			0x048
+#define SDIO_PRESENT_STATE1			0x04c
+#define SDIO_HOST_CTRL				0x050
+#define SDIO_BLK_GAP_CTRL			0x054
+#define SDIO_CLK_CTRL				0x058
+#define SDIO_SW_RESET				0x05c
+#define SDIO_NOR_INTR_STATUS		0x060
+#define SDIO_ERR_INTR_STATUS		0x064
+#define SDIO_NOR_STATUS_EN			0x068
+#define SDIO_ERR_STATUS_EN			0x06c
+#define SDIO_NOR_INTR_EN			0x070
+#define SDIO_ERR_INTR_EN			0x074
+#define SDIO_AUTOCMD12_ERR_STATUS	0x078
+#define SDIO_CURR_BYTE_LEFT			0x07c
+#define SDIO_CURR_BLK_LEFT			0x080
+#define SDIO_AUTOCMD12_ARG_LOW		0x084
+#define SDIO_AUTOCMD12_ARG_HI		0x088
+#define SDIO_AUTOCMD12_INDEX		0x08c
+#define SDIO_AUTO_RSP(i)			(0x090 + ((i)<<2))
+#define SDIO_AUTO_RSP0				0x090
+#define SDIO_AUTO_RSP1				0x094
+#define SDIO_AUTO_RSP2				0x098
+#define SDIO_CLK_DIV				0x128
+
+#define WINDOW_CTRL(i)				(0x108 + ((i) << 3))
+#define WINDOW_BASE(i)				(0x10c + ((i) << 3))
+
+/* SDIO_PRESENT_STATE */
+#define CARD_BUSY				(1 << 1)
+#define CMD_INHIBIT				(1 << 0)
+#define CMD_TXACTIVE			(1 << 8)
+#define CMD_RXACTIVE			(1 << 9)
+#define CMD_AUTOCMD12ACTIVE		(1 << 14)
+#define CMD_BUS_BUSY			(CMD_AUTOCMD12ACTIVE |	\
+								CMD_RXACTIVE |	\
+								CMD_TXACTIVE |	\
+								CMD_INHIBIT |	\
+								CARD_BUSY)
+
+/*
+ * SDIO_CMD
+ */
+
+#define SDIO_CMD_RSP_NONE				(0 << 0)
+#define SDIO_CMD_RSP_136				(1 << 0)
+#define SDIO_CMD_RSP_48					(2 << 0)
+#define SDIO_CMD_RSP_48BUSY				(3 << 0)
+
+#define SDIO_CMD_CHECK_DATACRC16		(1 << 2)
+#define SDIO_CMD_CHECK_CMDCRC			(1 << 3)
+#define SDIO_CMD_INDX_CHECK				(1 << 4)
+#define SDIO_CMD_DATA_PRESENT			(1 << 5)
+#define SDIO_UNEXPECTED_RESP			(1 << 7)
+
+#define SDIO_CMD_INDEX(x)				((x) << 8)
+
+/*
+ * SDIO_XFER_MODE
+ */
+
+#define SDIO_XFER_MODE_STOP_CLK			(1 << 5)
+#define SDIO_XFER_MODE_HW_WR_DATA_EN	(1 << 1)
+#define SDIO_XFER_MODE_AUTO_CMD12		(1 << 2)
+#define SDIO_XFER_MODE_INT_CHK_EN		(1 << 3)
+#define SDIO_XFER_MODE_TO_HOST			(1 << 4)
+#define SDIO_XFER_MODE_DMA				(0 << 6)
+
+/*
+ * SDIO_HOST_CTRL
+ */
+
+#define SDIO_HOST_CTRL_PUSH_PULL_EN 		(1 << 0)
+
+#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY 	(0 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY 	(1 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO 	(2 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC 	(3 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_MASK	 	(3 << 1)
+
+#define SDIO_HOST_CTRL_BIG_ENDIAN 		(1 << 3)
+#define SDIO_HOST_CTRL_LSB_FIRST 		(1 << 4)
+#define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT 	(0 << 9)
+#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS 	(1 << 9)
+#define SDIO_HOST_CTRL_HI_SPEED_EN 		(1 << 10)
+
+#define SDIO_HOST_CTRL_TMOUT_MAX 		0xf
+#define SDIO_HOST_CTRL_TMOUT_MASK 		(0xf << 11)
+#define SDIO_HOST_CTRL_TMOUT(x) 		((x) << 11)
+#define SDIO_HOST_CTRL_TMOUT_EN 		(1 << 15)
+
+/*
+ * SDIO_SW_RESET
+ */
+
+#define SDIO_SW_RESET_NOW			(1 << 8)
+
+/*
+ * Normal interrupt status bits
+ */
+
+#define SDIO_NOR_ERROR				(1 << 15)
+#define SDIO_NOR_UNEXP_RSP			(1 << 14)
+#define SDIO_NOR_AUTOCMD12_DONE		(1 << 13)
+#define SDIO_NOR_SUSPEND_ON			(1 << 12)
+#define SDIO_NOR_LMB_FF_8W_AVAIL	(1 << 11)
+#define SDIO_NOR_LMB_FF_8W_FILLED	(1 << 10)
+#define SDIO_NOR_READ_WAIT_ON		(1 << 9)
+#define SDIO_NOR_CARD_INT			(1 << 8)
+#define SDIO_NOR_READ_READY			(1 << 5)
+#define SDIO_NOR_WRITE_READY		(1 << 4)
+#define SDIO_NOR_DMA_INI			(1 << 3)
+#define SDIO_NOR_BLK_GAP_EVT		(1 << 2)
+#define SDIO_NOR_XFER_DONE			(1 << 1)
+#define SDIO_NOR_CMD_DONE			(1 << 0)
+
+/*
+ * Error status bits
+ */
+
+#define SDIO_ERR_CRC_STATUS			(1 << 14)
+#define SDIO_ERR_CRC_STARTBIT		(1 << 13)
+#define SDIO_ERR_CRC_ENDBIT			(1 << 12)
+#define SDIO_ERR_RESP_TBIT			(1 << 11)
+#define SDIO_ERR_XFER_SIZE			(1 << 10)
+#define SDIO_ERR_CMD_STARTBIT		(1 << 9)
+#define SDIO_ERR_AUTOCMD12			(1 << 8)
+#define SDIO_ERR_DATA_ENDBIT		(1 << 6)
+#define SDIO_ERR_DATA_CRC			(1 << 5)
+#define SDIO_ERR_DATA_TIMEOUT		(1 << 4)
+#define SDIO_ERR_CMD_INDEX			(1 << 3)
+#define SDIO_ERR_CMD_ENDBIT			(1 << 2)
+#define SDIO_ERR_CMD_CRC			(1 << 1)
+#define SDIO_ERR_CMD_TIMEOUT		(1 << 0)
+#define SDIO_POLL_MASK 				0xffff /* enable all for polling */
+
+#define MMC_BLOCK_SIZE                  512
+
+/*
+ * CMD12 error status bits
+ */
+
+#define SDIO_AUTOCMD12_ERR_NOTEXE		(1 << 0)
+#define SDIO_AUTOCMD12_ERR_TIMEOUT		(1 << 1)
+#define SDIO_AUTOCMD12_ERR_CRC			(1 << 2)
+#define SDIO_AUTOCMD12_ERR_ENDBIT		(1 << 3)
+#define SDIO_AUTOCMD12_ERR_INDEX		(1 << 4)
+#define SDIO_AUTOCMD12_ERR_RESP_T_BIT		(1 << 5)
+#define SDIO_AUTOCMD12_ERR_RESP_STARTBIT	(1 << 6)
+
+#define MMC_RSP_PRESENT	(1 << 0)
+#define MMC_RSP_136	(1 << 1)		/* 136 bit response */
+#define MMC_RSP_CRC	(1 << 2)		/* expect valid crc */
+#define MMC_RSP_BUSY	(1 << 3)		/* card may send busy */
+#define MMC_RSP_OPCODE	(1 << 4)		/* response contains opcode */
+
+#define MMC_BUSMODE_OPENDRAIN	1
+#define MMC_BUSMODE_PUSHPULL	2
+
+#define MMC_BUS_WIDTH_1		0
+#define MMC_BUS_WIDTH_4		2
+#define MMC_BUS_WIDTH_8		3
+
+#define MMC_CAP_4_BIT_DATA	(1 << 0)	/* Can the host do 4 bit transfers */
+#define MMC_CAP_MMC_HIGHSPEED	(1 << 1)	/* Can do MMC high-speed timing */
+#define MMC_CAP_SD_HIGHSPEED	(1 << 2)	/* Can do SD high-speed timing */
+#define MMC_CAP_SDIO_IRQ	(1 << 3)	/* Can signal pending SDIO IRQs */
+#define MMC_CAP_SPI		(1 << 4)	/* Talks only SPI protocols */
+#define MMC_CAP_NEEDS_POLL	(1 << 5)	/* Needs polling for card-detection */
+#define MMC_CAP_8_BIT_DATA	(1 << 6)	/* Can the host do 8 bit transfers */
+
+#define MMC_CAP_NONREMOVABLE	(1 << 8)	/* Nonremovable e.g. eMMC */
+#define MMC_CAP_WAIT_WHILE_BUSY	(1 << 9)	/* Waits while card is busy */
+#define MMC_CAP_ERASE		(1 << 10)	/* Allow erase/trim commands */
+#define MMC_CAP_1_8V_DDR	(1 << 11)	/* can support */
+						/* DDR mode at 1.8V */
+#define MMC_CAP_1_2V_DDR	(1 << 12)	/* can support */
+						/* DDR mode@1.2V */
+#define MMC_CAP_POWER_OFF_CARD	(1 << 13)	/* Can power off after boot */
+#define MMC_CAP_BUS_WIDTH_TEST	(1 << 14)	/* CMD14/CMD19 bus width ok */
+#define MMC_CAP_UHS_SDR12	(1 << 15)	/* Host supports UHS SDR12 mode */
+#define MMC_CAP_UHS_SDR25	(1 << 16)	/* Host supports UHS SDR25 mode */
+#define MMC_CAP_UHS_SDR50	(1 << 17)	/* Host supports UHS SDR50 mode */
+#define MMC_CAP_UHS_SDR104	(1 << 18)	/* Host supports UHS SDR104 mode */
+#define MMC_CAP_UHS_DDR50	(1 << 19)	/* Host supports UHS DDR50 mode */
+#define MMC_CAP_DRIVER_TYPE_A	(1 << 23)	/* Host supports Driver Type A */
+#define MMC_CAP_DRIVER_TYPE_C	(1 << 24)	/* Host supports Driver Type C */
+#define MMC_CAP_DRIVER_TYPE_D	(1 << 25)	/* Host supports Driver Type D */
+#define MMC_CAP_CMD23		(1 << 30)	/* CMD23 supported. */
+#define MMC_CAP_HW_RESET	(1 << 31)	/* Hardware reset */
+
+/*
+ * Functions prototypes
+ */
+
+static int mrvl_mmc_setup_data(struct mmc_data *data);
+static int mrvl_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data);
+static void mvsd_power_up(void);
+static void mvsd_power_down(void);
+static u32 mrvl_mmc_get_base_clock(void);
+static void mrvl_mmc_set_clk(uint clock);
+static void mrvl_mmc_set_bus(unsigned int bus);
+static void mrvl_mmc_set_ios(struct mmc *mmc);
+static int mrvl_mmc_init(struct mmc *mmc);
+int mrvl_mmc_initialize(bd_t *bis);
+
+#endif /* __MRVL_MMC_H__ */