From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maarten Lankhorst Date: Fri, 12 Jul 2013 07:54:57 +0000 Subject: Re: [patch] drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800() Message-Id: <51DFB651.9020008@canonical.com> List-Id: References: <20130712063329.GA29320@longonot.mountain> In-Reply-To: <20130712063329.GA29320@longonot.mountain> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Dan Carpenter Cc: David Airlie , kernel-janitors@vger.kernel.org, Ben Skeggs , dri-devel@lists.freedesktop.org Op 12-07-13 08:33, Dan Carpenter schreef: > We care about the upper 32 bits here so we have to use 1ULL instead of 1 > to avoid a shift wrapping bug. > > Signed-off-by: Dan Carpenter > > diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c > index 64dca26..fe67415 100644 > --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c > +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c > @@ -1039,7 +1039,7 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv) > } while (!tpcnr[gpc]); > tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; > > - tpc_set |= 1 << ((gpc * 8) + tpc); > + tpc_set |= 1ULL << ((gpc * 8) + tpc); > } > > nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set)); Reviewed-by: Maarten Lankhorst Any other code in nouveau that looks bugged? From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maarten Lankhorst Subject: Re: [patch] drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800() Date: Fri, 12 Jul 2013 09:54:57 +0200 Message-ID: <51DFB651.9020008@canonical.com> References: <20130712063329.GA29320@longonot.mountain> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20130712063329.GA29320@longonot.mountain> Sender: kernel-janitors-owner@vger.kernel.org To: Dan Carpenter Cc: David Airlie , kernel-janitors@vger.kernel.org, Ben Skeggs , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org Op 12-07-13 08:33, Dan Carpenter schreef: > We care about the upper 32 bits here so we have to use 1ULL instead of 1 > to avoid a shift wrapping bug. > > Signed-off-by: Dan Carpenter > > diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c > index 64dca26..fe67415 100644 > --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c > +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c > @@ -1039,7 +1039,7 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv) > } while (!tpcnr[gpc]); > tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; > > - tpc_set |= 1 << ((gpc * 8) + tpc); > + tpc_set |= 1ULL << ((gpc * 8) + tpc); > } > > nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set)); Reviewed-by: Maarten Lankhorst Any other code in nouveau that looks bugged?