Re: [Qemu-devel] [PATCH] pc: limit 64 bit hole to 2G by default

["Andreas Färber" <afaerber@suse.de>]

Hi,

Am 24.07.2013 08:01, schrieb Michael S. Tsirkin:
> It turns out that some 32 bit windows guests crash
> if 64 bit PCI hole size is >2G.
> Limit it to 2G for piix and q35 by default,
> add properties to let management override the hole size.
> 
> Examples:
> -global i440FX-pcihost.pci_hole64_size=137438953472
> 
> -global q35-pcihost.pci_hole64_size=137438953472
> 
> Reported-by: Igor Mammedov <imammedo@redhat.com>,
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> ---
>  hw/i386/pc.c              | 35 ++++++++++++++++++++---------------
>  hw/i386/pc_piix.c         | 14 +-------------
>  hw/pci-host/piix.c        | 42 ++++++++++++++++++++++++++++++++++--------
>  hw/pci-host/q35.c         | 29 +++++++++++++++++------------
>  include/hw/i386/pc.h      |  7 +++++--
>  include/hw/pci-host/q35.h |  1 +
>  6 files changed, 78 insertions(+), 50 deletions(-)
[...]
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 7fb2fb1..963b3d8 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -40,6 +41,7 @@
>  
>  typedef struct I440FXState {
>      PCIHostState parent_obj;
> +    uint64_t pci_hole64_size;
>  } I440FXState;
>  
>  #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
> @@ -234,9 +236,9 @@ static PCIBus *i440fx_common_init(const char *device_name,
>                                    hwaddr pci_hole_start,
>                                    hwaddr pci_hole_size,
>                                    hwaddr pci_hole64_start,
> -                                  hwaddr pci_hole64_size,
>                                    MemoryRegion *pci_address_space,
> -                                  MemoryRegion *ram_memory)
> +                                  MemoryRegion *ram_memory,
> +                                  PcGuestInfo *guest_info)
>  {
>      DeviceState *dev;
>      PCIBus *b;
> @@ -245,15 +247,31 @@ static PCIBus *i440fx_common_init(const char *device_name,
>      PIIX3State *piix3;
>      PCII440FXState *f;
>      unsigned i;
> +    I440FXState *i440fx;
>  
>      dev = qdev_create(NULL, "i440FX-pcihost");
>      s = PCI_HOST_BRIDGE(dev);
> +    i440fx = OBJECT_CHECK(I440FXState, dev, "i440FX-pcihost");

If we're lacking a macro for this, please define one. E.g.:
#define TYPE_I440FX "i440FX-pcihost"
#define I440FX(obj) OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX)
above I440FXState.

i440fx = I440FX(dev);

So far was unused due to PCI_HOST_BRIDGE(), I guess.

>      b = pci_bus_new(dev, NULL, pci_address_space,
>                      address_space_io, 0, TYPE_PCI_BUS);
>      s->bus = b;
>      object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
>      qdev_init_nofail(dev);
>  
> +    if (guest_info) {
> +        /* Set PCI window size the way seabios has always done it. */
> +        /* Power of 2 so bios can cover it with a single MTRR */
> +        if (ram_size <= 0x80000000)
> +            guest_info->pci_info.w32.begin = 0x80000000;
> +        else if (ram_size <= 0xc0000000)
> +            guest_info->pci_info.w32.begin = 0xc0000000;
> +        else
> +            guest_info->pci_info.w32.begin = 0xe0000000;
> +
> +        pc_init_pci_info(&guest_info->pci_info,
> +                         pci_hole64_start, i440fx->pci_hole64_size);
> +    }
> +
>      d = pci_create_simple(b, 0, device_name);
>      *pi440fx_state = I440FX_PCI_DEVICE(d);
>      f = *pi440fx_state;
> @@ -265,8 +283,8 @@ static PCIBus *i440fx_common_init(const char *device_name,
>      memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
>      memory_region_init_alias(&f->pci_hole_64bit, OBJECT(d), "pci-hole64",
>                               f->pci_address_space,
> -                             pci_hole64_start, pci_hole64_size);
> -    if (pci_hole64_size) {
> +                             pci_hole64_start, i440fx->pci_hole64_size);
> +    if (i440fx->pci_hole64_size) {
>          memory_region_add_subregion(f->system_memory, pci_hole64_start,
>                                      &f->pci_hole_64bit);
>      }
> @@ -322,8 +340,8 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
>                      hwaddr pci_hole_start,
>                      hwaddr pci_hole_size,
>                      hwaddr pci_hole64_start,
> -                    hwaddr pci_hole64_size,
> -                    MemoryRegion *pci_memory, MemoryRegion *ram_memory)
> +                    MemoryRegion *pci_memory, MemoryRegion *ram_memory,
> +                    PcGuestInfo *guest_info)
>  
>  {
>      PCIBus *b;
> @@ -332,8 +350,9 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
>                             piix3_devfn, isa_bus, pic,
>                             address_space_mem, address_space_io, ram_size,
>                             pci_hole_start, pci_hole_size,
> -                           pci_hole64_start, pci_hole64_size,
> -                           pci_memory, ram_memory);
> +                           pci_hole64_start,
> +                           pci_memory, ram_memory,
> +                           guest_info);
>      return b;
>  }
>  
> @@ -645,6 +664,12 @@ static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
>      return "0000";
>  }
>  
> +static Property i440fx_props[] = {
> +    DEFINE_PROP_UINT64("pci_hole64_size", I440FXState,

"pci-hole64-size"? Same for q35.

> +                       pci_hole64_size, 0x1ULL << 31),
> +    DEFINE_PROP_END_OF_LIST(),
> +};
> +
>  static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -655,6 +680,7 @@ static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
>      k->init = i440fx_pcihost_initfn;
>      dc->fw_name = "pci";
>      dc->no_user = 1;
> +    dc->props = i440fx_props;
>  }
>  
>  static const TypeInfo i440fx_pcihost_info = {
> diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
> index c761a43..4dd7ca4 100644
> --- a/hw/pci-host/q35.c
> +++ b/hw/pci-host/q35.c
> @@ -73,6 +74,8 @@ static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
>  static Property mch_props[] = {
>      DEFINE_PROP_UINT64("MCFG", Q35PCIHost, host.base_addr,
>                          MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
> +    DEFINE_PROP_UINT64("pci_hole64_size", Q35PCIHost,
> +                       mch.pci_hole64_size, 0x1ULL << 31),
>      DEFINE_PROP_END_OF_LIST(),
>  };
>  
[snip]

Do we need compat_props for pc-*-0.15 and earlier?

Regards,
Andreas

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