From: "Andreas Färber" <afaerber@suse.de>
To: qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>
Cc: qemu-ppc <qemu-ppc@nongnu.org>, Alexander Graf <agraf@suse.de>,
Don Koch <dkoch@verizon.com>,
"Michael S. Tsirkin" <mst@redhat.com>
Subject: Re: [Qemu-devel] [PATCH qom-next v2 1/4] pci-bridge: Turn PCIBridge into abstract QOM type
Date: Sat, 27 Jul 2013 02:37:28 +0200 [thread overview]
Message-ID: <51F31648.3090003@suse.de> (raw)
In-Reply-To: <1374532568-28051-2-git-send-email-afaerber@suse.de>
Am 23.07.2013 00:36, schrieb Andreas Färber:
> Introduce TYPE_PCI_BRIDGE as base type and use PCI_BRIDGE() casts.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> hw/pci-bridge/dec.c | 4 ++--
> hw/pci-bridge/i82801b11.c | 6 +++---
> hw/pci-bridge/ioh3420.c | 18 ++++++++---------
> hw/pci-bridge/pci_bridge_dev.c | 10 +++++-----
> hw/pci-bridge/xio3130_downstream.c | 18 ++++++++---------
> hw/pci-bridge/xio3130_upstream.c | 19 +++++++++---------
> hw/pci-host/apb.c | 4 ++--
> hw/pci/pci.c | 2 +-
> hw/pci/pci_bridge.c | 40 +++++++++++++++++++++++++++-----------
> hw/pci/pcie.c | 2 +-
> include/hw/pci/pci_bus.h | 7 ++++++-
> 11 files changed, 77 insertions(+), 53 deletions(-)
>
> diff --git a/hw/pci-bridge/dec.c b/hw/pci-bridge/dec.c
> index efc07c4..e5e3be8 100644
> --- a/hw/pci-bridge/dec.c
> +++ b/hw/pci-bridge/dec.c
> @@ -74,7 +74,7 @@ static void dec_21154_pci_bridge_class_init(ObjectClass *klass, void *data)
>
> static const TypeInfo dec_21154_pci_bridge_info = {
> .name = "dec-21154-p2p-bridge",
> - .parent = TYPE_PCI_DEVICE,
> + .parent = TYPE_PCI_BRIDGE,
> .instance_size = sizeof(PCIBridge),
> .class_init = dec_21154_pci_bridge_class_init,
> };
> @@ -86,7 +86,7 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)
>
> dev = pci_create_multifunction(parent_bus, devfn, false,
> "dec-21154-p2p-bridge");
> - br = DO_UPCAST(PCIBridge, dev, dev);
> + br = PCI_BRIDGE(dev);
> pci_bridge_map_irq(br, "DEC 21154 PCI-PCI bridge", dec_map_irq);
> qdev_init_nofail(&dev->qdev);
> return pci_bridge_get_sec_bus(br);
> diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c
> index b98bfb0..88f489a 100644
> --- a/hw/pci-bridge/i82801b11.c
> +++ b/hw/pci-bridge/i82801b11.c
> @@ -91,7 +91,7 @@ static void i82801b11_bridge_class_init(ObjectClass *klass, void *data)
>
> static const TypeInfo i82801b11_bridge_info = {
> .name = "i82801b11-bridge",
> - .parent = TYPE_PCI_DEVICE,
> + .parent = TYPE_PCI_BRIDGE,
> .instance_size = sizeof(I82801b11Bridge),
> .class_init = i82801b11_bridge_class_init,
> };
> @@ -107,8 +107,8 @@ PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus)
> if (!d) {
> return NULL;
> }
> - br = DO_UPCAST(PCIBridge, dev, d);
> - qdev = &br->dev.qdev;
> + br = PCI_BRIDGE(d);
> + qdev = DEVICE(d);
>
> snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
> pci_bridge_map_irq(br, buf, pci_swizzle_map_irq_fn);
> diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c
> index bb541eb..728f658 100644
> --- a/hw/pci-bridge/ioh3420.c
> +++ b/hw/pci-bridge/ioh3420.c
> @@ -92,7 +92,7 @@ static void ioh3420_reset(DeviceState *qdev)
>
> static int ioh3420_initfn(PCIDevice *d)
> {
> - PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
> + PCIBridge *br = PCI_BRIDGE(d);
> PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
> PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
> int rc;
> @@ -148,7 +148,7 @@ err_bridge:
>
> static void ioh3420_exitfn(PCIDevice *d)
> {
> - PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
> + PCIBridge *br = PCI_BRIDGE(d);
> PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
> PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
>
> @@ -171,9 +171,9 @@ PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,
> if (!d) {
> return NULL;
> }
> - br = DO_UPCAST(PCIBridge, dev, d);
> + br = PCI_BRIDGE(d);
>
> - qdev = &br->dev.qdev;
> + qdev = DEVICE(d);
> pci_bridge_map_irq(br, bus_name, map_irq);
> qdev_prop_set_uint8(qdev, "port", port);
> qdev_prop_set_uint8(qdev, "chassis", chassis);
> @@ -190,8 +190,8 @@ static const VMStateDescription vmstate_ioh3420 = {
> .minimum_version_id_old = 1,
> .post_load = pcie_cap_slot_post_load,
> .fields = (VMStateField[]) {
> - VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
> - VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
> + VMSTATE_PCIE_DEVICE(port.br.parent_obj, PCIESlot),
> + VMSTATE_STRUCT(port.br.parent_obj.exp.aer_log, PCIESlot, 0,
> vmstate_pcie_aer_log, PCIEAERLog),
> VMSTATE_END_OF_LIST()
> }
> @@ -202,8 +202,8 @@ static Property ioh3420_properties[] = {
> DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
> DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
> DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
> - port.br.dev.exp.aer_log.log_max,
> - PCIE_AER_LOG_MAX_DEFAULT),
> + port.br.parent_obj.exp.aer_log.log_max,
> + PCIE_AER_LOG_MAX_DEFAULT),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> @@ -228,7 +228,7 @@ static void ioh3420_class_init(ObjectClass *klass, void *data)
>
> static const TypeInfo ioh3420_info = {
> .name = "ioh3420",
> - .parent = TYPE_PCI_DEVICE,
> + .parent = TYPE_PCI_BRIDGE,
> .instance_size = sizeof(PCIESlot),
> .class_init = ioh3420_class_init,
> };
> diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c
> index 5f11323..00d2382 100644
> --- a/hw/pci-bridge/pci_bridge_dev.c
> +++ b/hw/pci-bridge/pci_bridge_dev.c
> @@ -38,7 +38,7 @@ typedef struct PCIBridgeDev PCIBridgeDev;
>
> static int pci_bridge_dev_initfn(PCIDevice *dev)
> {
> - PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
> + PCIBridge *br = PCI_BRIDGE(dev);
> PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
> int err;
>
> @@ -81,7 +81,7 @@ bridge_error:
>
> static void pci_bridge_dev_exitfn(PCIDevice *dev)
> {
> - PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
> + PCIBridge *br = PCI_BRIDGE(dev);
> PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
> if (msi_present(dev)) {
> msi_uninit(dev);
> @@ -120,8 +120,8 @@ static Property pci_bridge_dev_properties[] = {
> static const VMStateDescription pci_bridge_dev_vmstate = {
> .name = "pci_bridge",
> .fields = (VMStateField[]) {
> - VMSTATE_PCI_DEVICE(bridge.dev, PCIBridgeDev),
> - SHPC_VMSTATE(bridge.dev.shpc, PCIBridgeDev),
> + VMSTATE_PCI_DEVICE(bridge.parent_obj, PCIBridgeDev),
> + SHPC_VMSTATE(bridge.parent_obj.shpc, PCIBridgeDev),
> VMSTATE_END_OF_LIST()
> }
> };
> @@ -145,7 +145,7 @@ static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)
>
> static const TypeInfo pci_bridge_dev_info = {
> .name = "pci-bridge",
> - .parent = TYPE_PCI_DEVICE,
> + .parent = TYPE_PCI_BRIDGE,
> .instance_size = sizeof(PCIBridgeDev),
> .class_init = pci_bridge_dev_class_init,
> };
> diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
> index 1810dd2..9acce3f 100644
> --- a/hw/pci-bridge/xio3130_downstream.c
> +++ b/hw/pci-bridge/xio3130_downstream.c
> @@ -56,7 +56,7 @@ static void xio3130_downstream_reset(DeviceState *qdev)
>
> static int xio3130_downstream_initfn(PCIDevice *d)
> {
> - PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
> + PCIBridge *br = PCI_BRIDGE(d);
> PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
> PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
> int rc;
> @@ -113,7 +113,7 @@ err_bridge:
>
> static void xio3130_downstream_exitfn(PCIDevice *d)
> {
> - PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
> + PCIBridge *br = PCI_BRIDGE(d);
> PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
> PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
>
> @@ -138,9 +138,9 @@ PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,
> if (!d) {
> return NULL;
> }
> - br = DO_UPCAST(PCIBridge, dev, d);
> + br = PCI_BRIDGE(d);
>
> - qdev = &br->dev.qdev;
> + qdev = DEVICE(d);
> pci_bridge_map_irq(br, bus_name, map_irq);
> qdev_prop_set_uint8(qdev, "port", port);
> qdev_prop_set_uint8(qdev, "chassis", chassis);
> @@ -157,8 +157,8 @@ static const VMStateDescription vmstate_xio3130_downstream = {
> .minimum_version_id_old = 1,
> .post_load = pcie_cap_slot_post_load,
> .fields = (VMStateField[]) {
> - VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
> - VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
> + VMSTATE_PCIE_DEVICE(port.br.parent_obj, PCIESlot),
> + VMSTATE_STRUCT(port.br.parent_obj.exp.aer_log, PCIESlot, 0,
> vmstate_pcie_aer_log, PCIEAERLog),
> VMSTATE_END_OF_LIST()
> }
> @@ -169,8 +169,8 @@ static Property xio3130_downstream_properties[] = {
> DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
> DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
> DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
> - port.br.dev.exp.aer_log.log_max,
> - PCIE_AER_LOG_MAX_DEFAULT),
> + port.br.parent_obj.exp.aer_log.log_max,
> + PCIE_AER_LOG_MAX_DEFAULT),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> @@ -195,7 +195,7 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
>
> static const TypeInfo xio3130_downstream_info = {
> .name = "xio3130-downstream",
> - .parent = TYPE_PCI_DEVICE,
> + .parent = TYPE_PCI_BRIDGE,
> .instance_size = sizeof(PCIESlot),
> .class_init = xio3130_downstream_class_init,
> };
> diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c
> index 8e0d97a..0bc1d05 100644
> --- a/hw/pci-bridge/xio3130_upstream.c
> +++ b/hw/pci-bridge/xio3130_upstream.c
> @@ -53,7 +53,7 @@ static void xio3130_upstream_reset(DeviceState *qdev)
>
> static int xio3130_upstream_initfn(PCIDevice *d)
> {
> - PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
> + PCIBridge *br = PCI_BRIDGE(d);
> PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
> int rc;
>
> @@ -118,9 +118,9 @@ PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,
> if (!d) {
> return NULL;
> }
> - br = DO_UPCAST(PCIBridge, dev, d);
> + br = PCI_BRIDGE(d);
>
> - qdev = &br->dev.qdev;
> + qdev = DEVICE(d);
> pci_bridge_map_irq(br, bus_name, map_irq);
> qdev_prop_set_uint8(qdev, "port", port);
> qdev_init_nofail(qdev);
> @@ -134,17 +134,18 @@ static const VMStateDescription vmstate_xio3130_upstream = {
> .minimum_version_id = 1,
> .minimum_version_id_old = 1,
> .fields = (VMStateField[]) {
> - VMSTATE_PCIE_DEVICE(br.dev, PCIEPort),
> - VMSTATE_STRUCT(br.dev.exp.aer_log, PCIEPort, 0, vmstate_pcie_aer_log,
> - PCIEAERLog),
> + VMSTATE_PCIE_DEVICE(br.parent_obj, PCIEPort),
> + VMSTATE_STRUCT(br.parent_obj.exp.aer_log, PCIEPort, 0,
> + vmstate_pcie_aer_log, PCIEAERLog),
> VMSTATE_END_OF_LIST()
> }
> };
>
> static Property xio3130_upstream_properties[] = {
> DEFINE_PROP_UINT8("port", PCIEPort, port, 0),
> - DEFINE_PROP_UINT16("aer_log_max", PCIEPort, br.dev.exp.aer_log.log_max,
> - PCIE_AER_LOG_MAX_DEFAULT),
> + DEFINE_PROP_UINT16("aer_log_max", PCIEPort,
> + br.parent_obj.exp.aer_log.log_max,
> + PCIE_AER_LOG_MAX_DEFAULT),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> @@ -169,7 +170,7 @@ static void xio3130_upstream_class_init(ObjectClass *klass, void *data)
>
> static const TypeInfo xio3130_upstream_info = {
> .name = "x3130-upstream",
> - .parent = TYPE_PCI_DEVICE,
> + .parent = TYPE_PCI_BRIDGE,
> .instance_size = sizeof(PCIEPort),
> .class_init = xio3130_upstream_class_init,
> };
> diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
> index 06ace08..0277aa0 100644
> --- a/hw/pci-host/apb.c
> +++ b/hw/pci-host/apb.c
> @@ -464,7 +464,7 @@ PCIBus *pci_apb_init(hwaddr special_base,
> /* APB secondary busses */
> pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,
> "pbm-bridge");
> - br = DO_UPCAST(PCIBridge, dev, pci_dev);
> + br = PCI_BRIDGE(pci_dev);
> pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
> pci_apb_map_irq);
> qdev_init_nofail(&pci_dev->qdev);
> @@ -472,7 +472,7 @@ PCIBus *pci_apb_init(hwaddr special_base,
>
> pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true,
> "pbm-bridge");
> - br = DO_UPCAST(PCIBridge, dev, pci_dev);
> + br = PCI_BRIDGE(pci_dev);
> pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
> pci_apb_map_irq);
> qdev_init_nofail(&pci_dev->qdev);
This needs the following fixup. Thanks to Paolo for adding and enabling
sparc64 qtests that uncovered this.
Andreas
diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
index 1e80556..870b05b 100644
--- a/hw/pci-host/apb.c
+++ b/hw/pci-host/apb.c
@@ -564,8 +564,7 @@ static void pbm_pci_bridge_class_init(ObjectClass
*klass, void *data)
static const TypeInfo pbm_pci_bridge_info = {
.name = "pbm-bridge",
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(PCIBridge),
+ .parent = TYPE_PCI_BRIDGE,
.class_init = pbm_pci_bridge_class_init,
};
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
next prev parent reply other threads:[~2013-07-27 0:37 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-22 22:36 [Qemu-devel] [PATCH qom-next v2 0/4] QOM'ification of pci-bridge types Andreas Färber
2013-07-22 22:36 ` [Qemu-devel] [PATCH qom-next v2 1/4] pci-bridge: Turn PCIBridge into abstract QOM type Andreas Färber
2013-07-25 20:15 ` Don Koch
2013-07-25 21:08 ` Michael S. Tsirkin
2013-07-27 0:37 ` Andreas Färber [this message]
2013-07-22 22:36 ` [Qemu-devel] [PATCH qom-next v2 2/4] pci-bridge-dev: QOM parent field cleanup Andreas Färber
2013-07-25 20:15 ` Don Koch
2013-07-22 22:36 ` [Qemu-devel] [PATCH qom-next v2 3/4] pci-bridge/i82801b11: Rename parent field Andreas Färber
2013-07-25 20:15 ` Don Koch
2013-07-22 22:36 ` [Qemu-devel] [PATCH qom-next v2 4/4] pcie_port: Turn PCIEPort and PCIESlot into abstract QOM types Andreas Färber
2013-07-25 20:15 ` Don Koch
2013-07-25 21:05 ` Michael S. Tsirkin
2013-07-28 11:50 ` [Qemu-devel] [PATCH qom-next v2 0/4] QOM'ification of pci-bridge types Andreas Färber
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