From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:46162) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V37sw-0007Y8-PI for qemu-devel@nongnu.org; Sat, 27 Jul 2013 13:02:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V37rr-0001gA-53 for qemu-devel@nongnu.org; Sat, 27 Jul 2013 13:01:25 -0400 Received: from cantor2.suse.de ([195.135.220.15]:40106 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V37gK-00063a-NM for qemu-devel@nongnu.org; Sat, 27 Jul 2013 12:49:24 -0400 Message-ID: <51F3FA0E.2050300@suse.de> Date: Sat, 27 Jul 2013 18:49:18 +0200 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1374941897-11956-1-git-send-email-hpoussin@reactos.org> In-Reply-To: <1374941897-11956-1-git-send-email-hpoussin@reactos.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH for-1.6] target-mips: do not raise exceptions when accessing invalid memory List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?B?SGVydsOpIFBvdXNzaW5lYXU=?= , Peter Crosthwaite , "Edgar E. Iglesias" Cc: Stefan Weil , qemu-devel@nongnu.org, Peter Jovanovic , Paolo Bonzini , Leon Alrae , Aurelien Jarno Am 27.07.2013 18:18, schrieb Herv=C3=A9 Poussineau: > c658b94f6e8c206c59d02aa6fbac285b86b53d2c ("cpu: Turn cpu_unassigned_acc= ess() > into a CPUState hook") made MIPS raise exceptions when accessing > invalid memory for data, by unconditionally calling CPUState unassigned= hook. >=20 > While this seems to be the right behaviour, this breaks a lot of guests > (Linux on Malta, NetBSD on Magnum...) which try to access not emulated = devices > and crash because they don't handle the data load/store exception. >=20 > Revert to previous behaviour by not handling the !is_exec case in MIPS = CPU hook. >=20 > Signed-off-by: Herv=C3=A9 Poussineau So before my refactoring the following targets called it in files... alpha: cputlb.c and memory.c microblaze: memory.c mips: cputlb.c sparc: cputlb.c and memory.c ... and now all four call it in both places, breaking mips. The proposed solution looks acceptable to me, but I am no mips expert; CC'ing Aur=C3=A9lien, Stefan and some Imagination guys. As a reminder, 1.6-rc0 is due on Monday. > --- >=20 > Another solution would be to add a big dummy memory regions on all MIPS= boards > to catch memory accesses and not raise an exception. However, this mean= s that > each MIPS board will have its own unassigned memory handler, different = from the > global QEMU one. sparc uses the empty_slot device to catch accesses to devices that we are not yet emulating IIUC. I.e., empty_slot_init(addr, size). Peter/Edgar, can you double-check whether calling the unassigned_access handler from cputlb.c rather than cpu_abort()ing is OK for microblaze? Thanks, Andreas > --- > target-mips/op_helper.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) >=20 > diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c > index 5cf1c3f..94f1692 100644 > --- a/target-mips/op_helper.c > +++ b/target-mips/op_helper.c > @@ -2156,7 +2156,8 @@ void mips_cpu_unassigned_access(CPUState *cs, hwa= ddr addr, > if (is_exec) { > helper_raise_exception(env, EXCP_IBE); > } else { > - helper_raise_exception(env, EXCP_DBE); > + qemu_log_mask(LOG_UNIMP, "should raise DBE exception " > + "due to accessing memory at %" HWADDR_PRIx "\n",= addr); > } > } > #endif /* !CONFIG_USER_ONLY */ >=20 --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg