From mboxrd@z Thu Jan  1 00:00:00 1970
From: Kenneth Graunke <kenneth@whitecape.org>
Subject: Re: [PATCH 2/2] drm/i915: Use Write-Through cacheing
 for the display plane on Iris
Date: Tue, 30 Jul 2013 10:39:27 -0700
Message-ID: <51F7FA4F.1090007@whitecape.org>
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To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org, Ben Widawsky <ben@bwidawsk.net>
List-Id: intel-gfx@lists.freedesktop.org

On 07/30/2013 09:58 AM, Chris Wilson wrote:
> Haswell GT3e has the unique feature of supporting Write-Through cacheing
> of objects within the eLLC. The purpose of this is to enable the display
> plane to remain coherent whilst objects lie resident in the eLLC - so
> that we in theory get the best of both worlds, perfect display and fast
> access.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ben Widawsky <ben@bwidawsk.net>

Awesome.  Thanks a ton for doing this, Chris!

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>