From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Lutomirski Subject: Re: [PATCH 1/2] drm/i915: Use Write-Through cacheing for the display plane on Iris Date: Fri, 02 Aug 2013 11:45:22 -0700 Message-ID: <51FBFE42.2000503@amacapital.net> References: <1375378795-1869-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-pb0-f53.google.com (mail-pb0-f53.google.com [209.85.160.53]) by gabe.freedesktop.org (Postfix) with ESMTP id 7469CE7A26 for ; Fri, 2 Aug 2013 11:45:24 -0700 (PDT) Received: by mail-pb0-f53.google.com with SMTP id up15so1009933pbc.12 for ; Fri, 02 Aug 2013 11:45:24 -0700 (PDT) In-Reply-To: <1375378795-1869-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On 08/01/2013 10:39 AM, Chris Wilson wrote: > Haswell GT3e has the unique feature of supporting Write-Through cacheing > of objects within the eLLC/LLC. The purpose of this is to enable the display > plane to remain coherent whilst objects lie resident in the eLLC/LLC - so > that we, in theory, get the best of both worlds, perfect display and fast > access. > > However, we still need to be careful as the CPU does not see the WT when > accessing the cache. In particular, this means that we need to flush the > cache lines after writing to an object through the CPU, and on > transitioning from a cached state to WT. > I'm planning on adding ioremap_wt, etc sometime soon (for an unrelated reason). Would this be useful here? If so, do you need it for real RAM (i.e. pages that the kernel considers to be direct-mappable RAM) or just for MMIO space? --Andy