From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36768) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6GSX-0005fN-Gh for qemu-devel@nongnu.org; Mon, 05 Aug 2013 04:48:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V6GSR-0000a3-HQ for qemu-devel@nongnu.org; Mon, 05 Aug 2013 04:48:09 -0400 Received: from goliath.siemens.de ([192.35.17.28]:32057) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6GSR-0000ZS-86 for qemu-devel@nongnu.org; Mon, 05 Aug 2013 04:48:03 -0400 Message-ID: <51FF66B3.3090409@siemens.com> Date: Mon, 05 Aug 2013 10:47:47 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <1374941897-11956-1-git-send-email-hpoussin@reactos.org> <51F4218A.1060802@weilnetz.de> <51F430F4.6020708@suse.de> <51F4345D.6080007@weilnetz.de> <51F6D213.8040506@weilnetz.de> <20130804220423.GA4167@ohm.aurel32.net> <51FF662B.7080706@suse.de> In-Reply-To: <51FF662B.7080706@suse.de> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH for-1.6] target-mips: do not raise exceptions when accessing invalid memory List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?ISO-8859-15?Q?Andreas_F=E4rber?= Cc: Stefan Weil , =?ISO-8859-15?Q?Herv=E9_Poussineau?= , qemu-devel@nongnu.org, =?ISO-8859-15?Q?Aur=E9lien_Jarno?= , Peter Maydell On 2013-08-05 10:45, Andreas F=E4rber wrote: > Am 05.08.2013 00:04, schrieb Aur=E9lien Jarno: >> On Mon, Jul 29, 2013 at 10:35:31PM +0200, Stefan Weil wrote: >>> Am 27.07.2013 22:58, schrieb Stefan Weil: >>>> Am 27.07.2013 22:43, schrieb Andreas F=E4rber: >>>>> Am 27.07.2013 21:37, schrieb Stefan Weil: >>>>>> Am 27.07.2013 19:43, schrieb Peter Maydell: >>>>>>> On 27 July 2013 17:18, Herv=E9 Poussineau = wrote: >>>>>>>> Another solution would be to add a big dummy memory regions on a= ll MIPS boards >>>>>>>> to catch memory accesses and not raise an exception. However, th= is means that >>>>>>>> each MIPS board will have its own unassigned memory handler, dif= ferent from the >>>>>>>> global QEMU one. >>>>>>> Better would be to at least provide fake RAZ/WI implementations o= f >>>>>>> devices for the boards, rather than making the dummy region cover >>>>>>> the whole of the address space. Not 1.6 material, though. >>> >>> >>> For MIPS Malta, Linux boot can be fixed by handling read access for t= wo >>> addresses: >>> >>> 0x1fbf8008 >>> 0x1bc80110 >>> >>> The corresponding definitions in the Linux kernel code seem to be the= se >>> lines: >>> >>> #define GCMP_BASE_ADDR 0x1fbf8000 >>> #define GCMP_ADDRSPACE_SZ (256 * 1024) >>> #define GCMP_GCB_GCMPB_OFS 0x0008 /* Global GCM= P >>> Base */ >>> >>> #define MSC01_BIU_REG_BASE 0x1bc80000 >>> #define MSC01_BIU_ADDRSPACE_SZ (256 * 1024) >>> #define MSC01_SC_CFG_OFS 0x0110 >>> >>> =3D> mips_malta.c needs a handler for reads of >>> (GCMP_BASE_ADDR + GCMP_GCB_GCMPB_OFS) and >>> (MSC01_BIU_REG_BASE + MSC01_SC_CFG_OFS). >> >> I don't think it would be correct to emulate them as this are not >> present on the real Malta board, at least for the model emulated by >> QEMU. Theses addresses correspond to the SMP controller, and is >> therefore only present when an SMP daughter card is installed. >> >> The Linux kernel probes theses addresses, and look if they return >> something consistent. If not the corresponding devices are latter >> ignored. >> >> The real hardware probably returns all 1 or all 0 for addresses not >> decoded to a device. This is what QEMU should model, and it should >> not trigger a DBE or IBE exception. > [snip] >=20 > Have you tested Jan's patches limiting the new unassigned read value -1 > to PIO? Yeah, this sounds a lot like another side effect of using unassigned_mem_ops for PIO... Jan --=20 Siemens AG, Corporate Technology, CT RTC ITP SES-DE Corporate Competence Center Embedded Linux