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From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: Weiwei Li <liweiwei@iscas.ac.cn>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, dbarboza@ventanamicro.com,
	wangjunqiang@iscas.ac.cn, lazyparser@gmail.com
Subject: Re: [PATCH v2 2/5] target/riscv: Update cur_pmmask/base when xl changes
Date: Fri, 31 Mar 2023 09:34:22 +0800	[thread overview]
Message-ID: <51afd8dd-be0c-045d-eabf-47e6d07eccbd@linux.alibaba.com> (raw)
In-Reply-To: <20230329032346.55185-3-liweiwei@iscas.ac.cn>


On 2023/3/29 11:23, Weiwei Li wrote:
> write_mstatus() can only change current xl when in debug mode.
> And we need update cur_pmmask/base in this case.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/csr.c | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d522efc0b6..43b9ad4500 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1277,8 +1277,15 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
>           mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
>       }
>       env->mstatus = mstatus;
> -    env->xl = cpu_recompute_xl(env);
>   
> +    /*
> +     * Except in debug mode, UXL/SXL can only be modified by higher
> +     * privilege mode. So xl will not be changed in normal mode.
> +     */
> +    if (env->debugger) {
> +        env->xl = cpu_recompute_xl(env);
> +        riscv_cpu_update_mask(env);
> +    }
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Zhiwei
>       return RISCV_EXCP_NONE;
>   }
>   


  reply	other threads:[~2023-03-31  1:34 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-29  3:23 [PATCH v2 0/5] target/riscv: Fix pointer mask related support Weiwei Li
2023-03-29  3:23 ` [PATCH v2 1/5] target/riscv: Fix pointer mask transformation for vector address Weiwei Li
2023-03-29  3:23 ` [PATCH v2 2/5] target/riscv: Update cur_pmmask/base when xl changes Weiwei Li
2023-03-31  1:34   ` LIU Zhiwei [this message]
2023-03-29  3:23 ` [PATCH v2 3/5] target/riscv: Sync cpu_pc before update badaddr Weiwei Li
2023-03-29 15:33   ` Richard Henderson
2023-03-30  0:53     ` liweiwei
2023-03-31  6:13   ` LIU Zhiwei
2023-03-29  3:23 ` [PATCH v2 4/5] target/riscv: Add support for PC-relative translation Weiwei Li
2023-03-29 16:27   ` Richard Henderson
2023-03-30  1:09     ` liweiwei
2023-03-30 17:07       ` Richard Henderson
2023-03-29  3:23 ` [PATCH v2 5/5] target/riscv: Add pointer mask support for instruction fetch Weiwei Li
2023-03-29 16:36   ` Richard Henderson
2023-03-30  1:10     ` liweiwei

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