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Thu, 12 Mar 2020 09:28:06 +0000 MIME-Version: 1.0 Date: Thu, 12 Mar 2020 09:28:06 +0000 From: Marc Zyngier To: Zenghui Yu Subject: Re: [PATCH v5 01/23] irqchip/gic-v3: Use SGIs without active state if offered In-Reply-To: <63f6530a-9369-31e6-88d0-5337173495b9@huawei.com> References: <20200304203330.4967-1-maz@kernel.org> <20200304203330.4967-2-maz@kernel.org> <63f6530a-9369-31e6-88d0-5337173495b9@huawei.com> Message-ID: <51b2c74fdbcca049cc01be6d78c7c693@kernel.org> X-Sender: maz@kernel.org User-Agent: Roundcube Webmail/1.3.10 X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, lorenzo.pieralisi@arm.com, jason@lakedaemon.net, rrichter@marvell.com, tglx@linutronix.de, eric.auger@redhat.com, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: Lorenzo Pieralisi , Jason Cooper , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Robert Richter , Thomas Gleixner , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Zenghui, On 2020-03-12 06:30, Zenghui Yu wrote: > Hi Marc, > > On 2020/3/5 4:33, Marc Zyngier wrote: >> To allow the direct injection of SGIs into a guest, the GICv4.1 >> architecture has to sacrifice the Active state so that SGIs look >> a lot like LPIs (they are injected by the same mechanism). >> >> In order not to break existing software, the architecture gives >> offers guests OSs the choice: SGIs with or without an active >> state. It is the hypervisors duty to honor the guest's choice. >> >> For this, the architecture offers a discovery bit indicating whether >> the GIC supports GICv4.1 SGIs (GICD_TYPER2.nASSGIcap), and another >> bit indicating whether the guest wants Active-less SGIs or not >> (controlled by GICD_CTLR.nASSGIreq). > > I still can't find the description of these two bits in IHI0069F. > Are they actually architected and will be available in the future > version of the spec? I want to confirm it again since this has a > great impact on the KVM code, any pointers? Damn. The bits *are* in the engineering spec version 19 (unfortunately not a public document, but I believe you should have access to it). If the bits have effectively been removed from the spec, I'll drop the GICv4.1 code from the 5.7 queue until we find a way to achieve the same level of support. I've emailed people inside ARM to find out. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FE4CC10DCE for ; Thu, 12 Mar 2020 09:28:38 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E5D332067C for ; Thu, 12 Mar 2020 09:28:37 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Thu, 12 Mar 2020 09:28:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584005288; bh=xIGhcP4cmy8ksAfngF2mgtlMwAvRWwnp7zQoi+vTB4E=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Ol9RmPgG6uECdyzvoJTJo5SYZdG3qUpPKzQsdoTc8vSPi02q+vlQsNS79HFJvFY0P 0Bt+3mFe1NYvQql0pNZYnoazTijrKPAIcTY1AT5Eu00rdYs4Ap8/DE67DiNqleKLci vvQIo661e24v88EVbUp5uC/4dVvXkB8QiCJNjk2E= Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1jCK8M-00CAj6-I0; Thu, 12 Mar 2020 09:28:06 +0000 MIME-Version: 1.0 Date: Thu, 12 Mar 2020 09:28:06 +0000 From: Marc Zyngier To: Zenghui Yu Subject: Re: [PATCH v5 01/23] irqchip/gic-v3: Use SGIs without active state if offered In-Reply-To: <63f6530a-9369-31e6-88d0-5337173495b9@huawei.com> References: <20200304203330.4967-1-maz@kernel.org> <20200304203330.4967-2-maz@kernel.org> <63f6530a-9369-31e6-88d0-5337173495b9@huawei.com> Message-ID: <51b2c74fdbcca049cc01be6d78c7c693@kernel.org> X-Sender: maz@kernel.org User-Agent: Roundcube Webmail/1.3.10 X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, lorenzo.pieralisi@arm.com, jason@lakedaemon.net, rrichter@marvell.com, tglx@linutronix.de, eric.auger@redhat.com, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200312_022809_825010_349EF84F X-CRM114-Status: GOOD ( 13.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lorenzo Pieralisi , Jason Cooper , kvm@vger.kernel.org, Suzuki K Poulose , linux-kernel@vger.kernel.org, Eric Auger , Robert Richter , James Morse , Julien Thierry , Thomas Gleixner , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Zenghui, On 2020-03-12 06:30, Zenghui Yu wrote: > Hi Marc, > > On 2020/3/5 4:33, Marc Zyngier wrote: >> To allow the direct injection of SGIs into a guest, the GICv4.1 >> architecture has to sacrifice the Active state so that SGIs look >> a lot like LPIs (they are injected by the same mechanism). >> >> In order not to break existing software, the architecture gives >> offers guests OSs the choice: SGIs with or without an active >> state. It is the hypervisors duty to honor the guest's choice. >> >> For this, the architecture offers a discovery bit indicating whether >> the GIC supports GICv4.1 SGIs (GICD_TYPER2.nASSGIcap), and another >> bit indicating whether the guest wants Active-less SGIs or not >> (controlled by GICD_CTLR.nASSGIreq). > > I still can't find the description of these two bits in IHI0069F. > Are they actually architected and will be available in the future > version of the spec? I want to confirm it again since this has a > great impact on the KVM code, any pointers? Damn. The bits *are* in the engineering spec version 19 (unfortunately not a public document, but I believe you should have access to it). If the bits have effectively been removed from the spec, I'll drop the GICv4.1 code from the 5.7 queue until we find a way to achieve the same level of support. I've emailed people inside ARM to find out. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09AC5C2BB1D for ; Thu, 12 Mar 2020 09:28:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DB12620724 for ; Thu, 12 Mar 2020 09:28:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584005292; bh=xIGhcP4cmy8ksAfngF2mgtlMwAvRWwnp7zQoi+vTB4E=; h=Date:From:To:Cc:Subject:In-Reply-To:References:List-ID:From; b=DXYyl42ztJ+mzu8zwbF1vsifXX+xOUk2S0gin7T9HouuCpQplb91KlT7n6l/siuEQ Lg+DUOLLkbMYnuu4lrIRwLZ0WAwVGr9K5j6gsCQp/8s3h5jkhvB6Pdv8g8iQr7Lfl9 bRo/FyWrMs/RzusLV4oAFUmoZzwqJyawSFEa1QT0= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726695AbgCLJ2J (ORCPT ); Thu, 12 Mar 2020 05:28:09 -0400 Received: from mail.kernel.org ([198.145.29.99]:47684 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725268AbgCLJ2I (ORCPT ); Thu, 12 Mar 2020 05:28:08 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 573C02067C; Thu, 12 Mar 2020 09:28:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584005288; bh=xIGhcP4cmy8ksAfngF2mgtlMwAvRWwnp7zQoi+vTB4E=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Ol9RmPgG6uECdyzvoJTJo5SYZdG3qUpPKzQsdoTc8vSPi02q+vlQsNS79HFJvFY0P 0Bt+3mFe1NYvQql0pNZYnoazTijrKPAIcTY1AT5Eu00rdYs4Ap8/DE67DiNqleKLci vvQIo661e24v88EVbUp5uC/4dVvXkB8QiCJNjk2E= Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1jCK8M-00CAj6-I0; Thu, 12 Mar 2020 09:28:06 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Thu, 12 Mar 2020 09:28:06 +0000 From: Marc Zyngier To: Zenghui Yu Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Lorenzo Pieralisi , Jason Cooper , Robert Richter , Thomas Gleixner , Eric Auger , James Morse , Julien Thierry , Suzuki K Poulose Subject: Re: [PATCH v5 01/23] irqchip/gic-v3: Use SGIs without active state if offered In-Reply-To: <63f6530a-9369-31e6-88d0-5337173495b9@huawei.com> References: <20200304203330.4967-1-maz@kernel.org> <20200304203330.4967-2-maz@kernel.org> <63f6530a-9369-31e6-88d0-5337173495b9@huawei.com> Message-ID: <51b2c74fdbcca049cc01be6d78c7c693@kernel.org> X-Sender: maz@kernel.org User-Agent: Roundcube Webmail/1.3.10 X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, lorenzo.pieralisi@arm.com, jason@lakedaemon.net, rrichter@marvell.com, tglx@linutronix.de, eric.auger@redhat.com, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hi Zenghui, On 2020-03-12 06:30, Zenghui Yu wrote: > Hi Marc, > > On 2020/3/5 4:33, Marc Zyngier wrote: >> To allow the direct injection of SGIs into a guest, the GICv4.1 >> architecture has to sacrifice the Active state so that SGIs look >> a lot like LPIs (they are injected by the same mechanism). >> >> In order not to break existing software, the architecture gives >> offers guests OSs the choice: SGIs with or without an active >> state. It is the hypervisors duty to honor the guest's choice. >> >> For this, the architecture offers a discovery bit indicating whether >> the GIC supports GICv4.1 SGIs (GICD_TYPER2.nASSGIcap), and another >> bit indicating whether the guest wants Active-less SGIs or not >> (controlled by GICD_CTLR.nASSGIreq). > > I still can't find the description of these two bits in IHI0069F. > Are they actually architected and will be available in the future > version of the spec? I want to confirm it again since this has a > great impact on the KVM code, any pointers? Damn. The bits *are* in the engineering spec version 19 (unfortunately not a public document, but I believe you should have access to it). If the bits have effectively been removed from the spec, I'll drop the GICv4.1 code from the 5.7 queue until we find a way to achieve the same level of support. I've emailed people inside ARM to find out. Thanks, M. -- Jazz is not dead. It just smells funny...