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From: Stefan Bader <stefan.bader@canonical.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: xiantao.zhang@intel.com,
	Suravee Suthikulanit <suravee.suthikulpanit@amd.com>,
	xen-devel@lists.xen.org
Subject: Re: [PATCH 1/1] x86/AMD: Fix setup ssss:bb:dd:f for d0 failed
Date: Thu, 08 Aug 2013 14:07:18 +0200	[thread overview]
Message-ID: <520389F6.5040501@canonical.com> (raw)
In-Reply-To: <5203A1FD02000078000EA430@nat28.tlf.novell.com>


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On 08.08.2013 13:49, Jan Beulich wrote:
>>>> On 08.08.13 at 13:12, Stefan Bader <stefan.bader@canonical.com> wrote:
>> On 07.08.2013 10:33, Stefan Bader wrote:
>> So I went ahead and modified Suravee's patch according to what I think Jan 
>> was suggesting.
> 
> Mostly.
> 
>> This seems to be working and preventing the messages without 
>> showing any immediately visible problems.
> 
> Question is - did you in particular try with a legacy PCI device
> behind a legacy PCI bridge? That's the main scenario where the
> bridge not having got mapped could result in problems (see my
> other reply to Suravee on this thread).
> 
> Jan
> 

Not sure whether I confuse things here. Would the VGA card be what you meant?

-Stefan

-[0000:00]-+-00.0  Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridg
e (external gfx0 port A) [1002:5a13]
           ...
           +-14.4-[04]----04.0  Matrox Electronics Systems Ltd. MGA G200eW
WPCM450 [102b:0532]

00:14.4 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 PCI to
PCI Bridge [1002:4384] (prog-if 01 [Subtractive decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR+ FastB2B- DisINTx-
	Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
	Latency: 64
	Bus: primary=00, secondary=04, subordinate=04, sec-latency=64
	I/O behind bridge: 0000f000-00000fff
	Memory behind bridge: fdf00000-fe7fffff
	Prefetchable memory behind bridge: fc000000-fcffffff
	Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort-
<MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-

04:04.0 VGA compatible controller [0300]: Matrox Electronics Systems Ltd. MGA
G200eW WPCM450 [102b:0532] (rev 0a) (prog-if 00 [VGA controller])
	Subsystem: Super Micro Computer Inc Device [15d9:a711]
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
	Latency: 64 (4000ns min, 8000ns max), Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 10
	Region 0: Memory at fc000000 (32-bit, prefetchable) [size=16M]
	Region 1: Memory at fdffc000 (32-bit, non-prefetchable) [size=16K]
	Region 2: Memory at fe000000 (32-bit, non-prefetchable) [size=8M]
	Expansion ROM at <unassigned> [disabled]
	Capabilities: [dc] Power Management version 1
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-




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  reply	other threads:[~2013-08-08 12:07 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-08-07  2:40 [PATCH 1/1] x86/AMD: Fix setup ssss:bb:dd:f for d0 failed suravee.suthikulpanit
2013-08-07  2:42 ` Suravee Suthikulanit
2013-08-07  8:33   ` Stefan Bader
2013-08-08 11:12     ` Stefan Bader
2013-08-08 11:49       ` Jan Beulich
2013-08-08 12:07         ` Stefan Bader [this message]
2013-08-08 12:29           ` Jan Beulich
2013-08-08 12:35             ` Stefan Bader
2013-08-07  7:33 ` Jan Beulich
2013-08-07 15:31   ` Suravee Suthikulanit
2013-08-07 15:42     ` Jan Beulich
2013-08-07 19:20       ` Suravee Suthikulanit
2013-08-08  6:38         ` Jan Beulich
2013-08-30  1:25           ` Suravee Suthikulpanit
2013-08-30  8:09             ` Jan Beulich
2013-08-31  0:03               ` Suravee Suthikulpanit
2013-08-07  9:34 ` Andrew Cooper
2013-08-07  9:57   ` Jan Beulich

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