From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: [PATCH] x86: use "R" constraint for fxsaveq/fxrstorq enforcement Date: Tue, 13 Aug 2013 18:02:11 +0100 Message-ID: <520A6693.9070607@citrix.com> References: <520A705E02000078000EB96B@nat28.tlf.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1562468861658081013==" Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1V9IDh-0001h4-OQ for xen-devel@lists.xenproject.org; Tue, 13 Aug 2013 17:17:21 +0000 In-Reply-To: <520A705E02000078000EB96B@nat28.tlf.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: xen-devel , Keir Fraser List-Id: xen-devel@lists.xenproject.org --===============1562468861658081013== Content-Type: multipart/alternative; boundary="------------090400040204020109030504" --------------090400040204020109030504 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit On 13/08/13 16:43, Jan Beulich wrote: > I became aware of this constraint's (referring to all legacy registers > in one go) existence by (accidentally) noticing Linux commit 82024135 > ("x86-64, fpu: Simplify constraints for fxsave/fxtstor"). > > Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper > > --- a/xen/arch/x86/i387.c > +++ b/xen/arch/x86/i387.c > @@ -96,8 +96,7 @@ static inline void fpu_fxrstor(struct vc > ".previous \n" > _ASM_EXTABLE(1b, 2b) > : > - : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4), > - "cdaSDb" (fpu_ctxt) ); > + : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4), "R" (fpu_ctxt) ); > break; > case 4: case 2: > asm volatile ( > @@ -162,7 +161,7 @@ static inline void fpu_fxsave(struct vcp > * addressing mode that doesn't require extended registers. > */ > asm volatile ( REX64_PREFIX "fxsave (%1)" > - : "=m" (*fpu_ctxt) : "cdaSDb" (fpu_ctxt) ); > + : "=m" (*fpu_ctxt) : "R" (fpu_ctxt) ); > > /* > * AMD CPUs don't save/restore FDP/FIP/FOP unless an exception > > > > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xen.org > http://lists.xen.org/xen-devel --------------090400040204020109030504 Content-Type: text/html; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit
On 13/08/13 16:43, Jan Beulich wrote:
I became aware of this constraint's (referring to all legacy registers
in one go) existence by (accidentally) noticing Linux commit 82024135
("x86-64, fpu: Simplify constraints for fxsave/fxtstor").

Signed-off-by: Jan Beulich <jbeulich@suse.com>

Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>


--- a/xen/arch/x86/i387.c
+++ b/xen/arch/x86/i387.c
@@ -96,8 +96,7 @@ static inline void fpu_fxrstor(struct vc
             ".previous                \n"
             _ASM_EXTABLE(1b, 2b)
             :
-            : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4),
-              "cdaSDb" (fpu_ctxt) );
+            : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4), "R" (fpu_ctxt) );
         break;
     case 4: case 2:
         asm volatile (
@@ -162,7 +161,7 @@ static inline void fpu_fxsave(struct vcp
          * addressing mode that doesn't require extended registers.
          */
         asm volatile ( REX64_PREFIX "fxsave (%1)"
-                       : "=m" (*fpu_ctxt) : "cdaSDb" (fpu_ctxt) );
+                       : "=m" (*fpu_ctxt) : "R" (fpu_ctxt) );
 
         /*
          * AMD CPUs don't save/restore FDP/FIP/FOP unless an exception






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