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Date:   Tue, 13 Aug 2013 20:43:51 +0200
From:   John Crispin <blogic@openwrt.org>
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To:     Mark Brown <broonie@kernel.org>
CC:     Gabor Juhos <juhosg@openwrt.org>, linux-spi@vger.kernel.org,
        linux-mips@linux-mips.org
Subject: Re: [PATCH 2/2] SPI: ralink: add Ralink SoC spi driver
References: <1376074288-29302-1-git-send-email-blogic@openwrt.org> <1376074288-29302-2-git-send-email-blogic@openwrt.org> <20130811132642.GB6427@sirena.org.uk>
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Hi Mark,

Thanks for the review, I will send a V2 tomorrow, I want to verify my 
changes on real HW first.

a few comments inline ...

> There is presumably a maximum transfer size here from the FIFO that is
> holding the data?
The hardware is not running in DMA/IRQ mode and hence it can only 
read/write 1 byte at a time.

> Set min_speed_hz in the spi_master and the core will check this for you.

it seems that min_speed is not handled by the core yet. I saw several 
drivers do minimum speed testing. I am leaving this code in the driver 
until there is a generic minimum speed check
> clk_prepare_enable(), and it'd be nice to use runtime PM and enable the
> clock only when doing transfers though that's not essential.
>

The clock is free running and always running.

     John