diff for duplicates of <520B6441.6030200@ti.com> diff --git a/a/1.txt b/N1/1.txt index c21de83..ec9d617 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -58,12 +58,12 @@ On Wednesday 14 August 2013 04:04 PM, Marc Zyngier wrote: >> + #address-cells = <1>; >> + #size-cells = <0>; >> + ->> + cpu@0 { +>> + cpu at 0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a15"; >> + reg = <0>; >> + }; ->> + cpu@1 { +>> + cpu at 1 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a15"; >> + reg = <1>; @@ -78,7 +78,7 @@ On Wednesday 14 August 2013 04:04 PM, Marc Zyngier wrote: >> + <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; >> + }; >> + ->> + gic: interrupt-controller@48211000 { +>> + gic: interrupt-controller at 48211000 { >> + compatible = "arm,cortex-a15-gic"; >> + interrupt-controller; >> + #interrupt-cells = <3>; diff --git a/a/content_digest b/N1/content_digest index c3102ed..e1f79e6 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,20 +1,9 @@ "ref\01376475929-26050-1-git-send-email-rnayak@ti.com\0" "ref\018ceeaca6539d2c2ef88bf5a560a77f3@www.loen.fr\0" - "From\0Rajendra Nayak <rnayak@ti.com>\0" - "Subject\0Re: [PATCH] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board\0" + "From\0rnayak@ti.com (Rajendra Nayak)\0" + "Subject\0[PATCH] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board\0" "Date\0Wed, 14 Aug 2013 16:34:33 +0530\0" - "To\0Marc Zyngier <marc.zyngier@arm.com>\0" - "Cc\0bcousson@baylibre.com" - mark.rutland@arm.com - nm@ti.com - paul@pwsan.com - khilman@linaro.org - R Sricharan <r.sricharan@ti.com> - tony@atomide.com - santosh.shilimkar@ti.com - Sourav Poddar <sourav.poddar@ti.com> - linux-omap@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Wednesday 14 August 2013 04:04 PM, Marc Zyngier wrote:\n" @@ -77,12 +66,12 @@ ">> + #address-cells = <1>;\n" ">> + #size-cells = <0>;\n" ">> +\n" - ">> + cpu@0 {\n" + ">> + cpu at 0 {\n" ">> + device_type = \"cpu\";\n" ">> + compatible = \"arm,cortex-a15\";\n" ">> + reg = <0>;\n" ">> + };\n" - ">> + cpu@1 {\n" + ">> + cpu at 1 {\n" ">> + device_type = \"cpu\";\n" ">> + compatible = \"arm,cortex-a15\";\n" ">> + reg = <1>;\n" @@ -97,7 +86,7 @@ ">> + <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;\n" ">> + };\n" ">> +\n" - ">> + gic: interrupt-controller@48211000 {\n" + ">> + gic: interrupt-controller at 48211000 {\n" ">> + compatible = \"arm,cortex-a15-gic\";\n" ">> + interrupt-controller;\n" ">> + #interrupt-cells = <3>;\n" @@ -113,4 +102,4 @@ "> \n" > M. -c6ace1e879d2a8efc75a64a35ea339f846323d09c0ad8fafced0085343f172e0 +37f485bb5eff3b5ff34f0d4be225e993ba956b5d64f34564f6954b605bcab850
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