diff for duplicates of <520B83B0.1010707@ti.com> diff --git a/a/1.txt b/N1/1.txt index ba44d81..8d92f77 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -236,12 +236,12 @@ ah, will fix. >> + #address-cells = <1>; >> + #size-cells = <0>; >> + ->> + cpu@0 { +>> + cpu at 0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a15"; >> + reg = <0>; >> + }; ->> + cpu@1 { +>> + cpu at 1 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a15"; >> + reg = <1>; @@ -256,7 +256,7 @@ ah, will fix. >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; >> + }; >> + ->> + gic: interrupt-controller@48211000 { +>> + gic: interrupt-controller at 48211000 { >> + compatible = "arm,cortex-a15-gic"; >> + interrupt-controller; >> + #interrupt-cells = <3>; @@ -297,13 +297,13 @@ ah, will fix. >> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; >> + ->> + counter32k: counter@4ae04000 { +>> + counter32k: counter at 4ae04000 { >> + compatible = "ti,omap-counter32k"; >> + reg = <0x4ae04000 0x40>; >> + ti,hwmods = "counter_32k"; >> + }; >> + ->> + dra7_pmx_core: pinmux@4a003400 { +>> + dra7_pmx_core: pinmux at 4a003400 { >> + compatible = "pinctrl-single"; >> + reg = <0x4a003400 0x0464>; >> + #address-cells = <1>; @@ -312,7 +312,7 @@ ah, will fix. >> + pinctrl-single,function-mask = <0x3fffffff>; >> + }; >> + ->> + sdma: dma-controller@4a056000 { +>> + sdma: dma-controller at 4a056000 { >> + compatible = "ti,omap4430-sdma"; >> + reg = <0x4a056000 0x1000>; >> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, @@ -324,7 +324,7 @@ ah, will fix. >> + #dma-requests = <127>; >> + }; >> + ->> + gpio1: gpio@4ae10000 { +>> + gpio1: gpio at 4ae10000 { >> + compatible = "ti,omap4-gpio"; >> + reg = <0x4ae10000 0x200>; >> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; @@ -335,7 +335,7 @@ ah, will fix. >> + #interrupt-cells = <1>; >> + }; >> + ->> + gpio2: gpio@48055000 { +>> + gpio2: gpio at 48055000 { >> + compatible = "ti,omap4-gpio"; >> + reg = <0x48055000 0x200>; >> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; @@ -346,7 +346,7 @@ ah, will fix. >> + #interrupt-cells = <1>; >> + }; >> + ->> + gpio3: gpio@48057000 { +>> + gpio3: gpio at 48057000 { >> + compatible = "ti,omap4-gpio"; >> + reg = <0x48057000 0x200>; >> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; @@ -357,7 +357,7 @@ ah, will fix. >> + #interrupt-cells = <1>; >> + }; >> + ->> + gpio4: gpio@48059000 { +>> + gpio4: gpio at 48059000 { >> + compatible = "ti,omap4-gpio"; >> + reg = <0x48059000 0x200>; >> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; @@ -368,7 +368,7 @@ ah, will fix. >> + #interrupt-cells = <1>; >> + }; >> + ->> + gpio5: gpio@4805b000 { +>> + gpio5: gpio at 4805b000 { >> + compatible = "ti,omap4-gpio"; >> + reg = <0x4805b000 0x200>; >> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; @@ -379,7 +379,7 @@ ah, will fix. >> + #interrupt-cells = <1>; >> + }; >> + ->> + gpio6: gpio@4805d000 { +>> + gpio6: gpio at 4805d000 { >> + compatible = "ti,omap4-gpio"; >> + reg = <0x4805d000 0x200>; >> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; @@ -390,7 +390,7 @@ ah, will fix. >> + #interrupt-cells = <1>; >> + }; >> + ->> + gpio7: gpio@48051000 { +>> + gpio7: gpio at 48051000 { >> + compatible = "ti,omap4-gpio"; >> + reg = <0x48051000 0x200>; >> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; @@ -401,7 +401,7 @@ ah, will fix. >> + #interrupt-cells = <1>; >> + }; >> + ->> + gpio8: gpio@48053000 { +>> + gpio8: gpio at 48053000 { >> + compatible = "ti,omap4-gpio"; >> + reg = <0x48053000 0x200>; >> + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; @@ -412,7 +412,7 @@ ah, will fix. >> + #interrupt-cells = <1>; >> + }; >> + ->> + uart1: serial@4806a000 { +>> + uart1: serial at 4806a000 { >> + compatible = "ti,omap4-uart"; >> + reg = <0x4806a000 0x100>; >> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; @@ -421,7 +421,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + uart2: serial@4806c000 { +>> + uart2: serial at 4806c000 { >> + compatible = "ti,omap4-uart"; >> + reg = <0x4806c000 0x100>; >> + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; @@ -430,7 +430,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + uart3: serial@48020000 { +>> + uart3: serial at 48020000 { >> + compatible = "ti,omap4-uart"; >> + reg = <0x48020000 0x100>; >> + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; @@ -439,7 +439,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + uart4: serial@4806e000 { +>> + uart4: serial at 4806e000 { >> + compatible = "ti,omap4-uart"; >> + reg = <0x4806e000 0x100>; >> + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; @@ -448,7 +448,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + uart5: serial@48066000 { +>> + uart5: serial at 48066000 { >> + compatible = "ti,omap4-uart"; >> + reg = <0x48066000 0x100>; >> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; @@ -457,7 +457,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + uart6: serial@48068000 { +>> + uart6: serial at 48068000 { >> + compatible = "ti,omap4-uart"; >> + reg = <0x48068000 0x100>; >> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; @@ -466,7 +466,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + uart7: serial@48420000 { +>> + uart7: serial at 48420000 { >> + compatible = "ti,omap4-uart"; >> + reg = <0x48420000 0x100>; >> + ti,hwmods = "uart7"; @@ -474,7 +474,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + uart8: serial@48422000 { +>> + uart8: serial at 48422000 { >> + compatible = "ti,omap4-uart"; >> + reg = <0x48422000 0x100>; >> + ti,hwmods = "uart8"; @@ -482,7 +482,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + uart9: serial@48424000 { +>> + uart9: serial at 48424000 { >> + compatible = "ti,omap4-uart"; >> + reg = <0x48424000 0x100>; >> + ti,hwmods = "uart9"; @@ -490,7 +490,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + uart10: serial@4ae2b000 { +>> + uart10: serial at 4ae2b000 { >> + compatible = "ti,omap4-uart"; >> + reg = <0x4ae2b000 0x100>; >> + ti,hwmods = "uart10"; @@ -498,7 +498,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + timer1: timer@4ae18000 { +>> + timer1: timer at 4ae18000 { >> + compatible = "ti,omap5430-timer"; >> + reg = <0x4ae18000 0x80>; >> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; @@ -506,28 +506,28 @@ ah, will fix. >> + ti,timer-alwon; >> + }; >> + ->> + timer2: timer@48032000 { +>> + timer2: timer at 48032000 { >> + compatible = "ti,omap5430-timer"; >> + reg = <0x48032000 0x80>; >> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; >> + ti,hwmods = "timer2"; >> + }; >> + ->> + timer3: timer@48034000 { +>> + timer3: timer at 48034000 { >> + compatible = "ti,omap5430-timer"; >> + reg = <0x48034000 0x80>; >> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; >> + ti,hwmods = "timer3"; >> + }; >> + ->> + timer4: timer@48036000 { +>> + timer4: timer at 48036000 { >> + compatible = "ti,omap5430-timer"; >> + reg = <0x48036000 0x80>; >> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; >> + ti,hwmods = "timer4"; >> + }; >> + ->> + timer5: timer@48820000 { +>> + timer5: timer at 48820000 { >> + compatible = "ti,omap5430-timer"; >> + reg = <0x48820000 0x80>; >> + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; @@ -535,7 +535,7 @@ ah, will fix. >> + ti,timer-dsp; >> + }; >> + ->> + timer6: timer@48822000 { +>> + timer6: timer at 48822000 { >> + compatible = "ti,omap5430-timer"; >> + reg = <0x48822000 0x80>; >> + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; @@ -544,7 +544,7 @@ ah, will fix. >> + ti,timer-pwm; >> + }; >> + ->> + timer7: timer@48824000 { +>> + timer7: timer at 48824000 { >> + compatible = "ti,omap5430-timer"; >> + reg = <0x48824000 0x80>; >> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; @@ -552,7 +552,7 @@ ah, will fix. >> + ti,timer-dsp; >> + }; >> + ->> + timer8: timer@48826000 { +>> + timer8: timer at 48826000 { >> + compatible = "ti,omap5430-timer"; >> + reg = <0x48826000 0x80>; >> + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; @@ -561,21 +561,21 @@ ah, will fix. >> + ti,timer-pwm; >> + }; >> + ->> + timer9: timer@4803e000 { +>> + timer9: timer at 4803e000 { >> + compatible = "ti,omap5430-timer"; >> + reg = <0x4803e000 0x80>; >> + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; >> + ti,hwmods = "timer9"; >> + }; >> + ->> + timer10: timer@48086000 { +>> + timer10: timer at 48086000 { >> + compatible = "ti,omap5430-timer"; >> + reg = <0x48086000 0x80>; >> + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; >> + ti,hwmods = "timer10"; >> + }; >> + ->> + timer11: timer@48088000 { +>> + timer11: timer at 48088000 { >> + compatible = "ti,omap5430-timer"; >> + reg = <0x48088000 0x80>; >> + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; @@ -583,42 +583,42 @@ ah, will fix. >> + ti,timer-pwm; >> + }; >> + ->> + timer13: timer@48828000 { +>> + timer13: timer at 48828000 { >> + compatible = "ti,omap5430-timer"; >> + reg = <0x48828000 0x80>; >> + ti,hwmods = "timer13"; >> + status = "disabled"; >> + }; >> + ->> + timer14: timer@4882a000 { +>> + timer14: timer at 4882a000 { >> + compatible = "ti,omap5430-timer"; >> + reg = <0x4882a000 0x80>; >> + ti,hwmods = "timer14"; >> + status = "disabled"; >> + }; >> + ->> + timer15: timer@4882c000 { +>> + timer15: timer at 4882c000 { >> + compatible = "ti,omap5430-timer"; >> + reg = <0x4882c000 0x80>; >> + ti,hwmods = "timer15"; >> + status = "disabled"; >> + }; >> + ->> + timer16: timer@4882e000 { +>> + timer16: timer at 4882e000 { >> + compatible = "ti,omap5430-timer"; >> + reg = <0x4882e000 0x80>; >> + ti,hwmods = "timer16"; >> + status = "disabled"; >> + }; >> + ->> + wdt2: wdt@4ae14000 { +>> + wdt2: wdt at 4ae14000 { >> + compatible = "ti,omap4-wdt"; >> + reg = <0x4ae14000 0x80>; >> + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; >> + ti,hwmods = "wd_timer2"; >> + }; >> + ->> + i2c1: i2c@48070000 { +>> + i2c1: i2c at 48070000 { >> + compatible = "ti,omap4-i2c"; >> + reg = <0x48070000 0x100>; >> + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; @@ -628,7 +628,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + i2c2: i2c@48072000 { +>> + i2c2: i2c at 48072000 { >> + compatible = "ti,omap4-i2c"; >> + reg = <0x48072000 0x100>; >> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; @@ -638,7 +638,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + i2c3: i2c@48060000 { +>> + i2c3: i2c at 48060000 { >> + compatible = "ti,omap4-i2c"; >> + reg = <0x48060000 0x100>; >> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; @@ -648,7 +648,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + i2c4: i2c@4807a000 { +>> + i2c4: i2c at 4807a000 { >> + compatible = "ti,omap4-i2c"; >> + reg = <0x4807a000 0x100>; >> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; @@ -658,7 +658,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + i2c5: i2c@4807c000 { +>> + i2c5: i2c at 4807c000 { >> + compatible = "ti,omap4-i2c"; >> + reg = <0x4807c000 0x100>; >> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; @@ -668,7 +668,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + mmc1: mmc@4809c000 { +>> + mmc1: mmc at 4809c000 { >> + compatible = "ti,omap4-hsmmc"; >> + reg = <0x4809c000 0x400>; >> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; @@ -680,7 +680,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + mmc2: mmc@480b4000 { +>> + mmc2: mmc at 480b4000 { >> + compatible = "ti,omap4-hsmmc"; >> + reg = <0x480b4000 0x400>; >> + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; @@ -691,7 +691,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + mmc3: mmc@480ad000 { +>> + mmc3: mmc at 480ad000 { >> + compatible = "ti,omap4-hsmmc"; >> + reg = <0x480ad000 0x400>; >> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; @@ -702,7 +702,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + mmc4: mmc@480d1000 { +>> + mmc4: mmc at 480d1000 { >> + compatible = "ti,omap4-hsmmc"; >> + reg = <0x480d1000 0x400>; >> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; @@ -713,7 +713,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + mcspi1: spi@48098000 { +>> + mcspi1: spi at 48098000 { >> + compatible = "ti,omap4-mcspi"; >> + reg = <0x48098000 0x200>; >> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; @@ -734,7 +734,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + mcspi2: spi@4809a000 { +>> + mcspi2: spi at 4809a000 { >> + compatible = "ti,omap4-mcspi"; >> + reg = <0x4809a000 0x200>; >> + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; @@ -750,7 +750,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + mcspi3: spi@480b8000 { +>> + mcspi3: spi at 480b8000 { >> + compatible = "ti,omap4-mcspi"; >> + reg = <0x480b8000 0x200>; >> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; @@ -763,7 +763,7 @@ ah, will fix. >> + status = "disabled"; >> + }; >> + ->> + mcspi4: spi@480ba000 { +>> + mcspi4: spi at 480ba000 { >> + compatible = "ti,omap4-mcspi"; >> + reg = <0x480ba000 0x200>; >> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N1/content_digest index 9456fea..ea85702 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,20 +1,9 @@ "ref\01376482244-7550-1-git-send-email-rnayak@ti.com\0" "ref\0520B7961.1080907@baylibre.com\0" - "From\0Rajendra Nayak <rnayak@ti.com>\0" - "Subject\0Re: [PATCH v2] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board\0" + "From\0rnayak@ti.com (Rajendra Nayak)\0" + "Subject\0[PATCH v2] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board\0" "Date\0Wed, 14 Aug 2013 18:48:40 +0530\0" - "To\0Benoit Cousson <bcousson@baylibre.com>\0" - "Cc\0tony@atomide.com" - linux-omap@vger.kernel.org - linux-arm-kernel@lists.infradead.org - marc.zyngier@arm.com - mark.rutland@arm.com - paul@pwsan.com - khilman@linaro.org - nm@ti.com - santosh.shilimkar@ti.com - R Sricharan <r.sricharan@ti.com> - " Sourav Poddar <sourav.poddar@ti.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Wednesday 14 August 2013 06:04 PM, Benoit Cousson wrote:\n" @@ -255,12 +244,12 @@ ">> + #address-cells = <1>;\n" ">> + #size-cells = <0>;\n" ">> +\n" - ">> + cpu@0 {\n" + ">> + cpu at 0 {\n" ">> + device_type = \"cpu\";\n" ">> + compatible = \"arm,cortex-a15\";\n" ">> + reg = <0>;\n" ">> + };\n" - ">> + cpu@1 {\n" + ">> + cpu at 1 {\n" ">> + device_type = \"cpu\";\n" ">> + compatible = \"arm,cortex-a15\";\n" ">> + reg = <1>;\n" @@ -275,7 +264,7 @@ ">> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;\n" ">> + };\n" ">> +\n" - ">> + gic: interrupt-controller@48211000 {\n" + ">> + gic: interrupt-controller at 48211000 {\n" ">> + compatible = \"arm,cortex-a15-gic\";\n" ">> + interrupt-controller;\n" ">> + #interrupt-cells = <3>;\n" @@ -316,13 +305,13 @@ ">> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,\n" ">> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;\n" ">> +\n" - ">> + counter32k: counter@4ae04000 {\n" + ">> + counter32k: counter at 4ae04000 {\n" ">> + compatible = \"ti,omap-counter32k\";\n" ">> + reg = <0x4ae04000 0x40>;\n" ">> + ti,hwmods = \"counter_32k\";\n" ">> + };\n" ">> +\n" - ">> + dra7_pmx_core: pinmux@4a003400 {\n" + ">> + dra7_pmx_core: pinmux at 4a003400 {\n" ">> + compatible = \"pinctrl-single\";\n" ">> + reg = <0x4a003400 0x0464>;\n" ">> + #address-cells = <1>;\n" @@ -331,7 +320,7 @@ ">> + pinctrl-single,function-mask = <0x3fffffff>;\n" ">> + };\n" ">> +\n" - ">> + sdma: dma-controller@4a056000 {\n" + ">> + sdma: dma-controller at 4a056000 {\n" ">> + compatible = \"ti,omap4430-sdma\";\n" ">> + reg = <0x4a056000 0x1000>;\n" ">> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -343,7 +332,7 @@ ">> + #dma-requests = <127>;\n" ">> + };\n" ">> +\n" - ">> + gpio1: gpio@4ae10000 {\n" + ">> + gpio1: gpio at 4ae10000 {\n" ">> + compatible = \"ti,omap4-gpio\";\n" ">> + reg = <0x4ae10000 0x200>;\n" ">> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -354,7 +343,7 @@ ">> + #interrupt-cells = <1>;\n" ">> + };\n" ">> +\n" - ">> + gpio2: gpio@48055000 {\n" + ">> + gpio2: gpio at 48055000 {\n" ">> + compatible = \"ti,omap4-gpio\";\n" ">> + reg = <0x48055000 0x200>;\n" ">> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -365,7 +354,7 @@ ">> + #interrupt-cells = <1>;\n" ">> + };\n" ">> +\n" - ">> + gpio3: gpio@48057000 {\n" + ">> + gpio3: gpio at 48057000 {\n" ">> + compatible = \"ti,omap4-gpio\";\n" ">> + reg = <0x48057000 0x200>;\n" ">> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -376,7 +365,7 @@ ">> + #interrupt-cells = <1>;\n" ">> + };\n" ">> +\n" - ">> + gpio4: gpio@48059000 {\n" + ">> + gpio4: gpio at 48059000 {\n" ">> + compatible = \"ti,omap4-gpio\";\n" ">> + reg = <0x48059000 0x200>;\n" ">> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -387,7 +376,7 @@ ">> + #interrupt-cells = <1>;\n" ">> + };\n" ">> +\n" - ">> + gpio5: gpio@4805b000 {\n" + ">> + gpio5: gpio at 4805b000 {\n" ">> + compatible = \"ti,omap4-gpio\";\n" ">> + reg = <0x4805b000 0x200>;\n" ">> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -398,7 +387,7 @@ ">> + #interrupt-cells = <1>;\n" ">> + };\n" ">> +\n" - ">> + gpio6: gpio@4805d000 {\n" + ">> + gpio6: gpio at 4805d000 {\n" ">> + compatible = \"ti,omap4-gpio\";\n" ">> + reg = <0x4805d000 0x200>;\n" ">> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -409,7 +398,7 @@ ">> + #interrupt-cells = <1>;\n" ">> + };\n" ">> +\n" - ">> + gpio7: gpio@48051000 {\n" + ">> + gpio7: gpio at 48051000 {\n" ">> + compatible = \"ti,omap4-gpio\";\n" ">> + reg = <0x48051000 0x200>;\n" ">> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -420,7 +409,7 @@ ">> + #interrupt-cells = <1>;\n" ">> + };\n" ">> +\n" - ">> + gpio8: gpio@48053000 {\n" + ">> + gpio8: gpio at 48053000 {\n" ">> + compatible = \"ti,omap4-gpio\";\n" ">> + reg = <0x48053000 0x200>;\n" ">> + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -431,7 +420,7 @@ ">> + #interrupt-cells = <1>;\n" ">> + };\n" ">> +\n" - ">> + uart1: serial@4806a000 {\n" + ">> + uart1: serial at 4806a000 {\n" ">> + compatible = \"ti,omap4-uart\";\n" ">> + reg = <0x4806a000 0x100>;\n" ">> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -440,7 +429,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + uart2: serial@4806c000 {\n" + ">> + uart2: serial at 4806c000 {\n" ">> + compatible = \"ti,omap4-uart\";\n" ">> + reg = <0x4806c000 0x100>;\n" ">> + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -449,7 +438,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + uart3: serial@48020000 {\n" + ">> + uart3: serial at 48020000 {\n" ">> + compatible = \"ti,omap4-uart\";\n" ">> + reg = <0x48020000 0x100>;\n" ">> + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -458,7 +447,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + uart4: serial@4806e000 {\n" + ">> + uart4: serial at 4806e000 {\n" ">> + compatible = \"ti,omap4-uart\";\n" ">> + reg = <0x4806e000 0x100>;\n" ">> + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -467,7 +456,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + uart5: serial@48066000 {\n" + ">> + uart5: serial at 48066000 {\n" ">> + compatible = \"ti,omap4-uart\";\n" ">> + reg = <0x48066000 0x100>;\n" ">> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -476,7 +465,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + uart6: serial@48068000 {\n" + ">> + uart6: serial at 48068000 {\n" ">> + compatible = \"ti,omap4-uart\";\n" ">> + reg = <0x48068000 0x100>;\n" ">> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -485,7 +474,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + uart7: serial@48420000 {\n" + ">> + uart7: serial at 48420000 {\n" ">> + compatible = \"ti,omap4-uart\";\n" ">> + reg = <0x48420000 0x100>;\n" ">> + ti,hwmods = \"uart7\";\n" @@ -493,7 +482,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + uart8: serial@48422000 {\n" + ">> + uart8: serial at 48422000 {\n" ">> + compatible = \"ti,omap4-uart\";\n" ">> + reg = <0x48422000 0x100>;\n" ">> + ti,hwmods = \"uart8\";\n" @@ -501,7 +490,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + uart9: serial@48424000 {\n" + ">> + uart9: serial at 48424000 {\n" ">> + compatible = \"ti,omap4-uart\";\n" ">> + reg = <0x48424000 0x100>;\n" ">> + ti,hwmods = \"uart9\";\n" @@ -509,7 +498,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + uart10: serial@4ae2b000 {\n" + ">> + uart10: serial at 4ae2b000 {\n" ">> + compatible = \"ti,omap4-uart\";\n" ">> + reg = <0x4ae2b000 0x100>;\n" ">> + ti,hwmods = \"uart10\";\n" @@ -517,7 +506,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + timer1: timer@4ae18000 {\n" + ">> + timer1: timer at 4ae18000 {\n" ">> + compatible = \"ti,omap5430-timer\";\n" ">> + reg = <0x4ae18000 0x80>;\n" ">> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -525,28 +514,28 @@ ">> + ti,timer-alwon;\n" ">> + };\n" ">> +\n" - ">> + timer2: timer@48032000 {\n" + ">> + timer2: timer at 48032000 {\n" ">> + compatible = \"ti,omap5430-timer\";\n" ">> + reg = <0x48032000 0x80>;\n" ">> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n" ">> + ti,hwmods = \"timer2\";\n" ">> + };\n" ">> +\n" - ">> + timer3: timer@48034000 {\n" + ">> + timer3: timer at 48034000 {\n" ">> + compatible = \"ti,omap5430-timer\";\n" ">> + reg = <0x48034000 0x80>;\n" ">> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;\n" ">> + ti,hwmods = \"timer3\";\n" ">> + };\n" ">> +\n" - ">> + timer4: timer@48036000 {\n" + ">> + timer4: timer at 48036000 {\n" ">> + compatible = \"ti,omap5430-timer\";\n" ">> + reg = <0x48036000 0x80>;\n" ">> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;\n" ">> + ti,hwmods = \"timer4\";\n" ">> + };\n" ">> +\n" - ">> + timer5: timer@48820000 {\n" + ">> + timer5: timer at 48820000 {\n" ">> + compatible = \"ti,omap5430-timer\";\n" ">> + reg = <0x48820000 0x80>;\n" ">> + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -554,7 +543,7 @@ ">> + ti,timer-dsp;\n" ">> + };\n" ">> +\n" - ">> + timer6: timer@48822000 {\n" + ">> + timer6: timer at 48822000 {\n" ">> + compatible = \"ti,omap5430-timer\";\n" ">> + reg = <0x48822000 0x80>;\n" ">> + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -563,7 +552,7 @@ ">> + ti,timer-pwm;\n" ">> + };\n" ">> +\n" - ">> + timer7: timer@48824000 {\n" + ">> + timer7: timer at 48824000 {\n" ">> + compatible = \"ti,omap5430-timer\";\n" ">> + reg = <0x48824000 0x80>;\n" ">> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -571,7 +560,7 @@ ">> + ti,timer-dsp;\n" ">> + };\n" ">> +\n" - ">> + timer8: timer@48826000 {\n" + ">> + timer8: timer at 48826000 {\n" ">> + compatible = \"ti,omap5430-timer\";\n" ">> + reg = <0x48826000 0x80>;\n" ">> + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -580,21 +569,21 @@ ">> + ti,timer-pwm;\n" ">> + };\n" ">> +\n" - ">> + timer9: timer@4803e000 {\n" + ">> + timer9: timer at 4803e000 {\n" ">> + compatible = \"ti,omap5430-timer\";\n" ">> + reg = <0x4803e000 0x80>;\n" ">> + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n" ">> + ti,hwmods = \"timer9\";\n" ">> + };\n" ">> +\n" - ">> + timer10: timer@48086000 {\n" + ">> + timer10: timer at 48086000 {\n" ">> + compatible = \"ti,omap5430-timer\";\n" ">> + reg = <0x48086000 0x80>;\n" ">> + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;\n" ">> + ti,hwmods = \"timer10\";\n" ">> + };\n" ">> +\n" - ">> + timer11: timer@48088000 {\n" + ">> + timer11: timer at 48088000 {\n" ">> + compatible = \"ti,omap5430-timer\";\n" ">> + reg = <0x48088000 0x80>;\n" ">> + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -602,42 +591,42 @@ ">> + ti,timer-pwm;\n" ">> + };\n" ">> +\n" - ">> + timer13: timer@48828000 {\n" + ">> + timer13: timer at 48828000 {\n" ">> + compatible = \"ti,omap5430-timer\";\n" ">> + reg = <0x48828000 0x80>;\n" ">> + ti,hwmods = \"timer13\";\n" ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + timer14: timer@4882a000 {\n" + ">> + timer14: timer at 4882a000 {\n" ">> + compatible = \"ti,omap5430-timer\";\n" ">> + reg = <0x4882a000 0x80>;\n" ">> + ti,hwmods = \"timer14\";\n" ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + timer15: timer@4882c000 {\n" + ">> + timer15: timer at 4882c000 {\n" ">> + compatible = \"ti,omap5430-timer\";\n" ">> + reg = <0x4882c000 0x80>;\n" ">> + ti,hwmods = \"timer15\";\n" ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + timer16: timer@4882e000 {\n" + ">> + timer16: timer at 4882e000 {\n" ">> + compatible = \"ti,omap5430-timer\";\n" ">> + reg = <0x4882e000 0x80>;\n" ">> + ti,hwmods = \"timer16\";\n" ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + wdt2: wdt@4ae14000 {\n" + ">> + wdt2: wdt at 4ae14000 {\n" ">> + compatible = \"ti,omap4-wdt\";\n" ">> + reg = <0x4ae14000 0x80>;\n" ">> + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;\n" ">> + ti,hwmods = \"wd_timer2\";\n" ">> + };\n" ">> +\n" - ">> + i2c1: i2c@48070000 {\n" + ">> + i2c1: i2c at 48070000 {\n" ">> + compatible = \"ti,omap4-i2c\";\n" ">> + reg = <0x48070000 0x100>;\n" ">> + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -647,7 +636,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + i2c2: i2c@48072000 {\n" + ">> + i2c2: i2c at 48072000 {\n" ">> + compatible = \"ti,omap4-i2c\";\n" ">> + reg = <0x48072000 0x100>;\n" ">> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -657,7 +646,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + i2c3: i2c@48060000 {\n" + ">> + i2c3: i2c at 48060000 {\n" ">> + compatible = \"ti,omap4-i2c\";\n" ">> + reg = <0x48060000 0x100>;\n" ">> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -667,7 +656,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + i2c4: i2c@4807a000 {\n" + ">> + i2c4: i2c at 4807a000 {\n" ">> + compatible = \"ti,omap4-i2c\";\n" ">> + reg = <0x4807a000 0x100>;\n" ">> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -677,7 +666,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + i2c5: i2c@4807c000 {\n" + ">> + i2c5: i2c at 4807c000 {\n" ">> + compatible = \"ti,omap4-i2c\";\n" ">> + reg = <0x4807c000 0x100>;\n" ">> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -687,7 +676,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + mmc1: mmc@4809c000 {\n" + ">> + mmc1: mmc at 4809c000 {\n" ">> + compatible = \"ti,omap4-hsmmc\";\n" ">> + reg = <0x4809c000 0x400>;\n" ">> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -699,7 +688,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + mmc2: mmc@480b4000 {\n" + ">> + mmc2: mmc at 480b4000 {\n" ">> + compatible = \"ti,omap4-hsmmc\";\n" ">> + reg = <0x480b4000 0x400>;\n" ">> + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -710,7 +699,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + mmc3: mmc@480ad000 {\n" + ">> + mmc3: mmc at 480ad000 {\n" ">> + compatible = \"ti,omap4-hsmmc\";\n" ">> + reg = <0x480ad000 0x400>;\n" ">> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -721,7 +710,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + mmc4: mmc@480d1000 {\n" + ">> + mmc4: mmc at 480d1000 {\n" ">> + compatible = \"ti,omap4-hsmmc\";\n" ">> + reg = <0x480d1000 0x400>;\n" ">> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -732,7 +721,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + mcspi1: spi@48098000 {\n" + ">> + mcspi1: spi at 48098000 {\n" ">> + compatible = \"ti,omap4-mcspi\";\n" ">> + reg = <0x48098000 0x200>;\n" ">> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -753,7 +742,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + mcspi2: spi@4809a000 {\n" + ">> + mcspi2: spi at 4809a000 {\n" ">> + compatible = \"ti,omap4-mcspi\";\n" ">> + reg = <0x4809a000 0x200>;\n" ">> + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -769,7 +758,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + mcspi3: spi@480b8000 {\n" + ">> + mcspi3: spi at 480b8000 {\n" ">> + compatible = \"ti,omap4-mcspi\";\n" ">> + reg = <0x480b8000 0x200>;\n" ">> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -782,7 +771,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + mcspi4: spi@480ba000 {\n" + ">> + mcspi4: spi at 480ba000 {\n" ">> + compatible = \"ti,omap4-mcspi\";\n" ">> + reg = <0x480ba000 0x200>;\n" ">> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -830,4 +819,4 @@ "> Benoit\n" > -6beeadf0f82d95e299888f94ae920cb27dcedc118a27fe2d003bf74b031233ac +457471d80e57475ef0538f55d88824283ec7b1c0126bdf4cdf36b607a8b95048
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.