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diff for duplicates of <5212211C.3050407@ti.com>

diff --git a/a/1.txt b/N1/1.txt
index 396ee82..439dd58 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -32,7 +32,7 @@ On 08/03/2013 05:16 PM, Tomasz Figa wrote:
 >> * published by the Free Software Foundation.
 >> + */
 >> +
->> +bandgap_fclk: bandgap_fclk@4a307888 {
+>> +bandgap_fclk: bandgap_fclk at 4a307888 {
 >> +	#clock-cells = <0>;
 >> +	compatible = "gate-clock";
 >> +	clocks = <&sys_32k_ck>;
@@ -89,7 +89,7 @@ On 08/03/2013 05:16 PM, Tomasz Figa wrote:
 >> * published by the Free Software Foundation.
 >> + */
 >> +
->> +div_ts_ck: div_ts_ck@4a307888 {
+>> +div_ts_ck: div_ts_ck at 4a307888 {
 >> +	#clock-cells = <0>;
 >> +	compatible = "divider-clock";
 >> +	clocks = <&l4_wkup_clk_mux_ck>;
@@ -99,7 +99,7 @@ On 08/03/2013 05:16 PM, Tomasz Figa wrote:
 >> +	bit-mask = <0x3>;
 >> +};
 >> +
->> +bandgap_ts_fclk: bandgap_ts_fclk@4a307888 {
+>> +bandgap_ts_fclk: bandgap_ts_fclk at 4a307888 {
 >> +	#clock-cells = <0>;
 >> +	compatible = "gate-clock";
 >> +	clocks = <&div_ts_ck>;
@@ -134,7 +134,7 @@ On 08/03/2013 05:16 PM, Tomasz Figa wrote:
 >> +	clock-frequency = <12000000>;
 >> +};
 >> +
->> +pad_clks_ck: pad_clks_ck@4a004108 {
+>> +pad_clks_ck: pad_clks_ck at 4a004108 {
 >> +	#clock-cells = <0>;
 >> +	compatible = "gate-clock";
 >> +	clocks = <&pad_clks_src_ck>;
@@ -160,7 +160,7 @@ On 08/03/2013 05:16 PM, Tomasz Figa wrote:
 >> +	clock-frequency = <12000000>;
 >> +};
 >> +
->> +slimbus_clk: slimbus_clk@4a004108 {
+>> +slimbus_clk: slimbus_clk at 4a004108 {
 >> +	#clock-cells = <0>;
 >> +	compatible = "gate-clock";
 >> +	clocks = <&slimbus_src_clk>;
@@ -216,7 +216,7 @@ On 08/03/2013 05:16 PM, Tomasz Figa wrote:
 >> +	clock-frequency = <38400000>;
 >> +};
 >> +
->> +sys_clkin_ck: sys_clkin_ck@4a306110 {
+>> +sys_clkin_ck: sys_clkin_ck at 4a306110 {
 >> +	#clock-cells = <0>;
 >> +	compatible = "mux-clock";
 >> +	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>,
@@ -256,7 +256,7 @@ On 08/03/2013 05:16 PM, Tomasz Figa wrote:
 >> +	clock-frequency = <60000000>;
 >> +};
 >> +
->> +abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
+>> +abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck at 4a306108 {
 >> +	#clock-cells = <0>;
 >> +	compatible = "mux-clock";
 >> +	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
@@ -265,7 +265,7 @@ On 08/03/2013 05:16 PM, Tomasz Figa wrote:
 >> +	bit-mask = <0x1>;
 >> +};
 >> +
->> +abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@4a30610c {
+>> +abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck at 4a30610c {
 >> +	#clock-cells = <0>;
 >> +	compatible = "mux-clock";
 >> +	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
@@ -273,7 +273,7 @@ On 08/03/2013 05:16 PM, Tomasz Figa wrote:
 >> +	bit-mask = <0x1>;
 >> +};
 >> +
->> +dpll_abe_ck: dpll_abe_ck@4a0041e0 {
+>> +dpll_abe_ck: dpll_abe_ck at 4a0041e0 {
 >> +	#clock-cells = <0>;
 >> +	compatible = "ti,omap4-dpll-m4xen-clock";
 >> +	clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
diff --git a/a/content_digest b/N1/content_digest
index eaf732d..fe528a8 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,18 +1,10 @@
  "ref\01375460751-23676-1-git-send-email-t-kristo@ti.com\0"
  "ref\01375460751-23676-7-git-send-email-t-kristo@ti.com\0"
  "ref\04452066.ogQpVHnZLL@flatron\0"
- "From\0Tero Kristo <t-kristo@ti.com>\0"
- "Subject\0Re: [PATCHv5 06/31] ARM: dts: omap4 clock data\0"
+ "From\0t-kristo@ti.com (Tero Kristo)\0"
+ "Subject\0[PATCHv5 06/31] ARM: dts: omap4 clock data\0"
  "Date\0Mon, 19 Aug 2013 16:43:56 +0300\0"
- "To\0Tomasz Figa <tomasz.figa@gmail.com>\0"
- "Cc\0linux-omap@vger.kernel.org"
-  paul@pwsan.com
-  tony@atomide.com
-  nm@ti.com
-  rnayak@ti.com
-  mturquette@linaro.org
-  linux-arm-kernel@lists.infradead.org
- " devicetree@vger.kernel.org\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "On 08/03/2013 05:16 PM, Tomasz Figa wrote:\n"
@@ -49,7 +41,7 @@
  ">> * published by the Free Software Foundation.\n"
  ">> + */\n"
  ">> +\n"
- ">> +bandgap_fclk: bandgap_fclk@4a307888 {\n"
+ ">> +bandgap_fclk: bandgap_fclk at 4a307888 {\n"
  ">> +\t#clock-cells = <0>;\n"
  ">> +\tcompatible = \"gate-clock\";\n"
  ">> +\tclocks = <&sys_32k_ck>;\n"
@@ -106,7 +98,7 @@
  ">> * published by the Free Software Foundation.\n"
  ">> + */\n"
  ">> +\n"
- ">> +div_ts_ck: div_ts_ck@4a307888 {\n"
+ ">> +div_ts_ck: div_ts_ck at 4a307888 {\n"
  ">> +\t#clock-cells = <0>;\n"
  ">> +\tcompatible = \"divider-clock\";\n"
  ">> +\tclocks = <&l4_wkup_clk_mux_ck>;\n"
@@ -116,7 +108,7 @@
  ">> +\tbit-mask = <0x3>;\n"
  ">> +};\n"
  ">> +\n"
- ">> +bandgap_ts_fclk: bandgap_ts_fclk@4a307888 {\n"
+ ">> +bandgap_ts_fclk: bandgap_ts_fclk at 4a307888 {\n"
  ">> +\t#clock-cells = <0>;\n"
  ">> +\tcompatible = \"gate-clock\";\n"
  ">> +\tclocks = <&div_ts_ck>;\n"
@@ -151,7 +143,7 @@
  ">> +\tclock-frequency = <12000000>;\n"
  ">> +};\n"
  ">> +\n"
- ">> +pad_clks_ck: pad_clks_ck@4a004108 {\n"
+ ">> +pad_clks_ck: pad_clks_ck at 4a004108 {\n"
  ">> +\t#clock-cells = <0>;\n"
  ">> +\tcompatible = \"gate-clock\";\n"
  ">> +\tclocks = <&pad_clks_src_ck>;\n"
@@ -177,7 +169,7 @@
  ">> +\tclock-frequency = <12000000>;\n"
  ">> +};\n"
  ">> +\n"
- ">> +slimbus_clk: slimbus_clk@4a004108 {\n"
+ ">> +slimbus_clk: slimbus_clk at 4a004108 {\n"
  ">> +\t#clock-cells = <0>;\n"
  ">> +\tcompatible = \"gate-clock\";\n"
  ">> +\tclocks = <&slimbus_src_clk>;\n"
@@ -233,7 +225,7 @@
  ">> +\tclock-frequency = <38400000>;\n"
  ">> +};\n"
  ">> +\n"
- ">> +sys_clkin_ck: sys_clkin_ck@4a306110 {\n"
+ ">> +sys_clkin_ck: sys_clkin_ck at 4a306110 {\n"
  ">> +\t#clock-cells = <0>;\n"
  ">> +\tcompatible = \"mux-clock\";\n"
  ">> +\tclocks = <&virt_12000000_ck>, <&virt_13000000_ck>,\n"
@@ -273,7 +265,7 @@
  ">> +\tclock-frequency = <60000000>;\n"
  ">> +};\n"
  ">> +\n"
- ">> +abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {\n"
+ ">> +abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck at 4a306108 {\n"
  ">> +\t#clock-cells = <0>;\n"
  ">> +\tcompatible = \"mux-clock\";\n"
  ">> +\tclocks = <&sys_clkin_ck>, <&sys_32k_ck>;\n"
@@ -282,7 +274,7 @@
  ">> +\tbit-mask = <0x1>;\n"
  ">> +};\n"
  ">> +\n"
- ">> +abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@4a30610c {\n"
+ ">> +abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck at 4a30610c {\n"
  ">> +\t#clock-cells = <0>;\n"
  ">> +\tcompatible = \"mux-clock\";\n"
  ">> +\tclocks = <&sys_clkin_ck>, <&sys_32k_ck>;\n"
@@ -290,7 +282,7 @@
  ">> +\tbit-mask = <0x1>;\n"
  ">> +};\n"
  ">> +\n"
- ">> +dpll_abe_ck: dpll_abe_ck@4a0041e0 {\n"
+ ">> +dpll_abe_ck: dpll_abe_ck at 4a0041e0 {\n"
  ">> +\t#clock-cells = <0>;\n"
  ">> +\tcompatible = \"ti,omap4-dpll-m4xen-clock\";\n"
  ">> +\tclocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;\n"
@@ -309,4 +301,4 @@
  "\n"
  -Tero
 
-0bfd82ee2f8abe3b33a79962fd58fb65ef9fa92c061145aa02118bf437511542
+2f4d73e25c3aaae8323ba983cf7a5eab473f4f76f0280b8a975887a4951a8061

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