From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.free-electrons.com (top.free-electrons.com [176.31.233.9]) by yocto-www.yoctoproject.org (Postfix) with ESMTP id DBDBFE0122C for ; Fri, 30 Aug 2013 00:54:35 -0700 (PDT) Received: by mail.free-electrons.com (Postfix, from userid 106) id 61867849; Fri, 30 Aug 2013 09:54:50 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.3.2 Received: from [192.168.1.53] (128-79-216-144.hfc.dyn.abo.bbox.fr [128.79.216.144]) by mail.free-electrons.com (Postfix) with ESMTPSA id E305681D; Fri, 30 Aug 2013 09:54:49 +0200 (CEST) Message-ID: <52204FB9.7020403@free-electrons.com> Date: Fri, 30 Aug 2013 09:54:33 +0200 From: Alexandre Belloni Organization: Free Electrons User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130803 Thunderbird/17.0.8 MIME-Version: 1.0 To: Mangaud Philippe-R49081 References: <1377536327-22919-1-git-send-email-alexandre.belloni@free-electrons.com> <1377536327-22919-3-git-send-email-alexandre.belloni@free-electrons.com> <1F1FCC0D09F8D74A800E2DC9C69FFD1A0A116AD5@039-SN2MPN1-011.039d.mgd.msft.net> In-Reply-To: <1F1FCC0D09F8D74A800E2DC9C69FFD1A0A116AD5@039-SN2MPN1-011.039d.mgd.msft.net> X-Enigmail-Version: 1.4.6 Cc: "meta-freescale@yoctoproject.org" , Maxime Ripard , "jimwall@q.com" , "brian@crystalfontz.com" Subject: Re: [meta-fsl-arm-extra][PATCHv3 2/4] imx-bootlets: add a recipe for barebox and cfa-10036 support X-BeenThere: meta-freescale@yoctoproject.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Usage and development list for the meta-fsl-* layers List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 30 Aug 2013 07:54:37 -0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Hi Philippe, On 30/08/2013 09:47, Mangaud Philippe-R49081 wrote: > Hello Alexandre, > > DDR settings are sensible and would require full stress test to validate, looks like you are changing the number of address pins and adding a CAS cycle for every imX28 board. Looks like your board got a Micron, wouldn't it make sense to add you own set of DDR setting instead of touching original Elpida from EVK ? This patch will only be used when building for the cfa-10036 anyway so I'm not sure this is worth the trouble. Regards -- Alexandre Belloni, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com