From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: [PATCH 1/2] x86: remove X86_INTEL_USERCOPY code Date: Fri, 30 Aug 2013 09:46:19 +0100 Message-ID: <52205BDB.3090903@citrix.com> References: <1377828849-18059-1-git-send-email-msw@amazon.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1VFKLx-0000f7-IJ for xen-devel@lists.xenproject.org; Fri, 30 Aug 2013 08:46:49 +0000 In-Reply-To: <1377828849-18059-1-git-send-email-msw@amazon.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Matt Wilson Cc: xen-devel@lists.xenproject.org, Keir Fraser , Jan Beulich List-Id: xen-devel@lists.xenproject.org On 30/08/13 03:14, Matt Wilson wrote: > Nothing defines CONFIG_X86_INTEL_USERCOPY, and as far as I can tell it > was never used even when Xen supported 32-bit x86. > > Signed-off-by: Matt Wilson And furthermore, turning it on would appear to result in a compile error as movsl_mask doesn't appear to exist anywhere, certainly nowhere I can find in the current tree. Reviewed-by: Andrew Cooper > --- > xen/arch/x86/cpu/intel.c | 21 --------------------- > 1 files changed, 0 insertions(+), 21 deletions(-) > > diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c > index 9b71d36..072ecbc 100644 > --- a/xen/arch/x86/cpu/intel.c > +++ b/xen/arch/x86/cpu/intel.c > @@ -18,13 +18,6 @@ > > #define select_idle_routine(x) ((void)0) > > -#ifdef CONFIG_X86_INTEL_USERCOPY > -/* > - * Alignment at which movsl is preferred for bulk memory copies. > - */ > -struct movsl_mask movsl_mask __read_mostly; > -#endif > - > static unsigned int probe_intel_cpuid_faulting(void) > { > uint64_t x; > @@ -229,20 +222,6 @@ static void __devinit init_intel(struct cpuinfo_x86 *c) > /* Work around errata */ > Intel_errata_workarounds(c); > > -#ifdef CONFIG_X86_INTEL_USERCOPY > - /* > - * Set up the preferred alignment for movsl bulk memory moves > - */ > - switch (c->x86) { > - case 6: /* PII/PIII only like movsl with 8-byte alignment */ > - movsl_mask.mask = 7; > - break; > - case 15: /* P4 is OK down to 8-byte alignment */ > - movsl_mask.mask = 7; > - break; > - } > -#endif > - > if ((c->x86 == 0xf && c->x86_model >= 0x03) || > (c->x86 == 0x6 && c->x86_model >= 0x0e)) > set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);