From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55286) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGWMp-00048R-AI for qemu-devel@nongnu.org; Mon, 02 Sep 2013 11:48:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGWMi-00086F-0o for qemu-devel@nongnu.org; Mon, 02 Sep 2013 11:48:39 -0400 Received: from cantor2.suse.de ([195.135.220.15]:57549 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGWMh-000868-NF for qemu-devel@nongnu.org; Mon, 02 Sep 2013 11:48:31 -0400 Message-ID: <5224B34B.6090307@suse.de> Date: Mon, 02 Sep 2013 17:48:27 +0200 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1378131189-25538-1-git-send-email-marcel.a@redhat.com> <1378131189-25538-4-git-send-email-marcel.a@redhat.com> <1378136553.2640.34.camel@localhost.localdomain> In-Reply-To: <1378136553.2640.34.camel@localhost.localdomain> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH RFC 3/3] hw/pci-host: catch acesses to unassigned pci addresses List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Marcel Apfelbaum Cc: Peter Maydell , Anthony Liguori , "Michael S. Tsirkin" , QEMU Developers , Paolo Bonzini Am 02.09.2013 17:42, schrieb Marcel Apfelbaum: > On Mon, 2013-09-02 at 15:39 +0100, Peter Maydell wrote: >> On 2 September 2013 15:13, Marcel Apfelbaum wrot= e: >>> Added a memory region that has negative priority and >>> extends over all the pci adddress space. This region will >>> "catch" all the accesses to the unassigned pci >>> addresses and it will be possible to emulate the >>> master abort scenario (When no device on the bus claims >>> the transaction). >>> >>> Signed-off-by: Marcel Apfelbaum >>> --- >>> hw/pci-host/piix.c | 8 ++++++++ >>> hw/pci-host/q35.c | 19 ++++++++++++++++--- >>> include/hw/pci-host/q35.h | 1 + >> >> This is happening at the wrong layer -- you want this memory >> region to be created and managed in the PCI core code so that >> we get correct PCI-spec behaviour for all our PCI controllers, >> not just the two x86 ones you've changed here.pci_address_space > I saw that the memory regions are part of the Host state and > duplicated for each host type(like pci_address_space).=20 > Question, why are not pci_address_space and pci_hole present > in a core layer? I would say, because that core layer didn't exist before I added it not too long ago. My focus was on fixing bugs at the time and getting PReP Raven PHB into shape for QOM. > I followed the existing code; from what you are saying > I understand that also the existing memory regions=20 > like the one mentioned above should be moved in > the core layer, right? Consider it all Work In Progress :) and feel free to move more fields and code there as you guys see fit. Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg